Searched refs:MAILBOX_INTERRUPT_0 (Results 1 – 2 of 2) sorted by relevance
147 tw32_mailbox2(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); in tg3_disable_ints()2027 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); in tg3_setup_hw()2028 tr32(MAILBOX_INTERRUPT_0); in tg3_setup_hw()2981 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, in tg3_ack_irqs()2987 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); in tg3_ack_irqs()
372 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ macro