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Searched refs:ISR_INT_TARGET_MASK_F5 (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/common/io/ntxn/
H A Dnx_hw_pci_regs.h98 #define ISR_INT_TARGET_MASK_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) macro
160 ISR_INT_TARGET_MASK_F5, \
/titanic_41/usr/src/uts/common/sys/fibre-channel/fca/qlc/
H A Dql_nx.h1049 #define ISR_INT_TARGET_MASK_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) macro
1110 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \