xref: /titanic_41/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_hw.h (revision d478d0a82b5f273f7eac89c8df47960d9d22820b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at
9  * http://www.opensource.org/licenses/cddl1.txt.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2004-2011 Emulex. All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _EMLXS_HW_H
28 #define	_EMLXS_HW_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 #define	MAX_VPORTS			256	/* Max virtual ports per HBA */
35 						/* (includes physical port) */
36 #define	MAX_VPORTS_LIMITED		101
37 
38 #define	FC_MAX_TRANSFER			0x40000	/* Max transfer size per */
39 						/* operation */
40 
41 #define	MAX_RINGS_AVAILABLE		4	/* # rings available */
42 #define	MAX_RINGS			4	/* Max # rings used */
43 
44 #define	PCB_SIZE			128
45 
46 #define	SLIM_IOCB_CMD_R0_ENTRIES	128	/* SLI FCP cmd ring entries  */
47 #define	SLIM_IOCB_RSP_R0_ENTRIES	128	/* SLI FCP rsp ring entries */
48 #define	SLIM_IOCB_CMD_R1_ENTRIES	128	/* SLI IP cmd ring entries   */
49 #define	SLIM_IOCB_RSP_R1_ENTRIES	128	/* SLI IP rsp ring entries  */
50 #define	SLIM_IOCB_CMD_R2_ENTRIES	128	/* SLI ELS cmd ring entries  */
51 #define	SLIM_IOCB_RSP_R2_ENTRIES	128	/* SLI ELS rspe ring entries */
52 #define	SLIM_IOCB_CMD_R3_ENTRIES	128	/* SLI CT cmd ring entries   */
53 #define	SLIM_IOCB_RSP_R3_ENTRIES	128	/* SLI CT rsp ring entries  */
54 
55 /*
56  * Total: 184 Cmd's + 184 Rsp's = 368
57  * Command and response entry counts are not required to be equal
58  */
59 
60 #define	SLIM_IOCB_CMD_ENTRIES		(SLIM_IOCB_CMD_R0_ENTRIES + \
61 					SLIM_IOCB_CMD_R1_ENTRIES + \
62 					SLIM_IOCB_CMD_R2_ENTRIES + \
63 					SLIM_IOCB_CMD_R3_ENTRIES)
64 
65 #define	SLIM_IOCB_RSP_ENTRIES		(SLIM_IOCB_RSP_R0_ENTRIES + \
66 					SLIM_IOCB_RSP_R1_ENTRIES + \
67 					SLIM_IOCB_RSP_R2_ENTRIES + \
68 					SLIM_IOCB_RSP_R3_ENTRIES)
69 
70 #define	SLIM_IOCB_ENTRIES		(SLIM_IOCB_CMD_ENTRIES + \
71 					SLIM_IOCB_RSP_ENTRIES)
72 
73 
74 /* SLI1 Definitions */
75 #define	SLI_SLIM1_SIZE			4096 /* Fixed size memory */
76 
77 
78 /* SLI2 Definitions */
79 #define	SLI2_IOCB_CMD_SIZE		32
80 #define	SLI2_IOCB_RSP_SIZE		32
81 #define	SLI2_IOCB_MAX_SIZE		((SLI2_IOCB_CMD_SIZE * \
82 					SLIM_IOCB_CMD_ENTRIES) + \
83 					(SLI2_IOCB_RSP_SIZE * \
84 					SLIM_IOCB_RSP_ENTRIES))
85 #define	SLI2_SLIM2_SIZE			(MBOX_SIZE + MBOX_EXTENSION_SIZE + \
86 					PCB_SIZE + SLI2_IOCB_MAX_SIZE)
87 
88 
89 /* SLI3 Definitions */
90 #define	SLI3_MAX_BDE			7
91 #define	SLI3_IOCB_CMD_SIZE		128
92 #define	SLI3_IOCB_RSP_SIZE		64
93 #define	SLI3_IOCB_MAX_SIZE		((SLI3_IOCB_CMD_SIZE * \
94 					SLIM_IOCB_CMD_ENTRIES) + \
95 					(SLI3_IOCB_RSP_SIZE * \
96 					SLIM_IOCB_RSP_ENTRIES))
97 #define	SLI3_SLIM2_SIZE			(MBOX_SIZE + MBOX_EXTENSION_SIZE + \
98 					PCB_SIZE + SLI3_IOCB_MAX_SIZE)
99 
100 #define	SLI_SLIM2_SIZE			SLI3_SLIM2_SIZE
101 #define	SLI_IOCB_MAX_SIZE		SLI3_IOCB_MAX_SIZE
102 
103 
104 /* These two are defined to indicate FCP cmd or non FCP cmd */
105 #define	FC_FCP_CMD		0
106 #define	FC_FCT_CMD		0
107 #define	FC_IP_CMD		1
108 #define	FC_ELS_CMD		2
109 #define	FC_CT_CMD		3
110 
111 #define	FC_NFCP_CMD		1	/* could be a bit mask */
112 
113 #define	FC_MAXRETRY		3	/* max retries for ELS commands */
114 #define	FC_FCP_RING		0	/* use ring 0 for FCP initiator cmds */
115 #define	FC_FCT_RING		0	/* use ring 0 for FCP target cmds */
116 
117 #define	FC_IP_RING		1	/* use ring 1 for IP commands */
118 #define	FC_ELS_RING		2	/* use ring 2 for ELS commands */
119 #define	FC_CT_RING		3	/* use ring 3 for CT commands */
120 
121 #define	FF_DEF_EDTOV		2000	/* Default E_D_TOV (2000ms) */
122 #define	FF_DEF_ALTOV		15	/* Default AL_TIME (15ms) */
123 #define	FF_DEF_RATOV		2	/* Default RA_TOV (2s) */
124 #define	FF_DEF_ARBTOV		1900	/* Default ARB_TOV (1900ms) */
125 #define	MAX_MSG_DATA		28	/* max msg data in CMD_ADAPTER_MSG */
126 					/* iocb */
127 #define	FF_REG_AREA_SIZE	256	/* size, in bytes, of i/o register */
128 					/* area */
129 
130 /*
131  * Miscellaneous stuff....
132  */
133 
134 #define	MAX_NODE_THROTTLE	2048
135 
136 /* HBA Mgmt */
137 #define	FDMI_DID		((uint32_t)0xfffffa)
138 #define	NAMESERVER_DID		((uint32_t)0xfffffc)
139 #define	SCR_DID			((uint32_t)0xfffffd)
140 #define	FABRIC_DID		((uint32_t)0xfffffe)
141 #define	BCAST_DID		((uint32_t)0xffffff)
142 #define	MASK_DID		((uint32_t)0xffffff)
143 #define	CT_DID_MASK		((uint32_t)0xffff00)
144 #define	FABRIC_DID_MASK		((uint32_t)0xfff000)
145 #define	WELL_KNOWN_DID_MASK	((uint32_t)0xfffff0)
146 
147 #define	EMLXS_MENLO_DID		((uint32_t)0x00fc0e)
148 
149 #define	OWN_CHIP	1	/* IOCB / Mailbox is owned by FireFly */
150 #define	OWN_HOST	0	/* IOCB / Mailbox is owned by Host */
151 #define	END_OF_CHAIN	0
152 
153 
154 /* defines for type field in fc header */
155 #define	EMLXS_MENLO_TYPE	0xFE
156 
157 /* defines for rctl field in fc header */
158 #define	FC_DEV_DATA	0x0
159 #define	FC_UNSOL_CTL	0x2
160 #define	FC_SOL_CTL	0x3
161 #define	FC_UNSOL_DATA	0x4
162 #define	FC_FCP_CMND	0x6
163 #define	FC_ELS_REQ	0x22
164 #define	FC_ELS_RSP	0x23
165 #define	FC_NET_HDR	0x20	/* network headers for Dfctl field */
166 
167 /*
168  * Common Transport structures and definitions
169  *
170  */
171 #define	EMLXS_COMMAND	0
172 #define	EMLXS_RESPONSE	1
173 
174 typedef union CtRevisionId
175 {
176 	/* Structure is in Big Endian format */
177 	struct
178 	{
179 		uint32_t	Revision:8;
180 		uint32_t	InId:24;
181 	} bits;
182 	uint32_t	word;
183 } CtRevisionId_t;
184 
185 typedef union CtCommandResponse
186 {
187 	/* Structure is in Big Endian format */
188 	struct
189 	{
190 		uint32_t	CmdRsp:16;
191 		uint32_t	Size:16;
192 	} bits;
193 	uint32_t	word;
194 } CtCommandResponse_t;
195 
196 typedef struct SliCtRequest
197 {
198 	/* Structure is in Big Endian format */
199 	CtRevisionId_t		RevisionId;
200 	uint8_t			FsType;
201 	uint8_t			FsSubType;
202 	uint8_t			Options;
203 	uint8_t			Rsrvd1;
204 	CtCommandResponse_t	CommandResponse;
205 	uint8_t			Rsrvd2;
206 	uint8_t			ReasonCode;
207 	uint8_t			Explanation;
208 	uint8_t			VendorUnique;
209 
210 	union
211 	{
212 		uint32_t	data;
213 		uint32_t	PortID;
214 
215 		struct gid
216 		{
217 			uint8_t	PortType;	/* for GID_PT requests */
218 			uint8_t	DomainScope;
219 			uint8_t	AreaScope;
220 			uint8_t	Fc4Type;	/* for GID_FT requests */
221 		} gid;
222 		struct rft
223 		{
224 			uint32_t	PortId;	/* For RFT_ID requests */
225 #ifdef EMLXS_BIG_ENDIAN
226 			uint32_t	rsvd0:16;
227 			uint32_t	rsvd1:7;
228 			uint32_t	fcpReg:1;	/* Type 8 */
229 			uint32_t	rsvd2:2;
230 			uint32_t	ipReg:1;	/* Type 5 */
231 			uint32_t	rsvd3:5;
232 #endif
233 #ifdef EMLXS_LITTLE_ENDIAN
234 			uint32_t	rsvd0:16;
235 			uint32_t	fcpReg:1;	/* Type 8 */
236 			uint32_t	rsvd1:7;
237 			uint32_t	rsvd3:5;
238 			uint32_t	ipReg:1;	/* Type 5 */
239 			uint32_t	rsvd2:2;
240 #endif
241 			uint32_t	rsvd[7];
242 		} rft;
243 
244 		struct rsnn
245 		{
246 			uint8_t		wwnn[8];
247 			uint8_t		snn_len;
248 			char		snn[256];
249 		} rsnn;
250 
251 		struct rspn
252 		{
253 			uint32_t	PortId;
254 			uint8_t		spn_len;
255 			char		spn[256];
256 		} rspn;
257 	} un;
258 } SliCtRequest_t;
259 typedef SliCtRequest_t SLI_CT_REQUEST;
260 
261 #define	SLI_CT_REVISION	1
262 
263 
264 /*
265  * FsType Definitions
266  */
267 
268 #define	SLI_CT_MANAGEMENT_SERVICE		0xFA
269 #define	SLI_CT_TIME_SERVICE			0xFB
270 #define	SLI_CT_DIRECTORY_SERVICE		0xFC
271 #define	SLI_CT_FABRIC_CONTROLLER_SERVICE	0xFD
272 
273 /*
274  * Directory Service Subtypes
275  */
276 
277 #define	SLI_CT_DIRECTORY_NAME_SERVER	0x02
278 
279 /*
280  * Response Codes
281  */
282 
283 #define	SLI_CT_RESPONSE_FS_RJT	0x8001
284 #define	SLI_CT_RESPONSE_FS_ACC	0x8002
285 
286 /*
287  * Reason Codes
288  */
289 
290 #define	SLI_CT_NO_ADDITIONAL_EXPL		0x0
291 #define	SLI_CT_INVALID_COMMAND			0x01
292 #define	SLI_CT_INVALID_VERSION			0x02
293 #define	SLI_CT_LOGICAL_ERROR			0x03
294 #define	SLI_CT_INVALID_IU_SIZE			0x04
295 #define	SLI_CT_LOGICAL_BUSY			0x05
296 #define	SLI_CT_PROTOCOL_ERROR			0x07
297 #define	SLI_CT_UNABLE_TO_PERFORM_REQ		0x09
298 #define	SLI_CT_REQ_NOT_SUPPORTED		0x0b
299 #define	SLI_CT_HBA_INFO_NOT_REGISTERED		0x10
300 #define	SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE	0x11
301 #define	SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN	0x12
302 #define	SLI_CT_HBA_ATTR_NOT_PRESENT		0x13
303 #define	SLI_CT_PORT_INFO_NOT_REGISTERED		0x20
304 #define	SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE	0x21
305 #define	SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN	0x22
306 #define	SLI_CT_VENDOR_UNIQUE			0xff
307 
308 /*
309  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
310  */
311 
312 #define	SLI_CT_NO_PORT_ID		0x01
313 #define	SLI_CT_NO_PORT_NAME		0x02
314 #define	SLI_CT_NO_NODE_NAME		0x03
315 #define	SLI_CT_NO_CLASS_OF_SERVICE	0x04
316 #define	SLI_CT_NO_IP_ADDRESS		0x05
317 #define	SLI_CT_NO_IPA			0x06
318 #define	SLI_CT_NO_FC4_TYPES		0x07
319 #define	SLI_CT_NO_SYMBOLIC_PORT_NAME	0x08
320 #define	SLI_CT_NO_SYMBOLIC_NODE_NAME	0x09
321 #define	SLI_CT_NO_PORT_TYPE		0x0A
322 #define	SLI_CT_ACCESS_DENIED		0x10
323 #define	SLI_CT_INVALID_PORT_ID		0x11
324 #define	SLI_CT_DATABASE_EMPTY		0x12
325 
326 #ifdef EMLXS_BIG_ENDIAN
327 #define	CT_CMD_MASK	0xffff0000
328 #endif
329 
330 #ifdef EMLXS_LITTLE_ENDIAN
331 #define	CT_CMD_MASK	0xffff
332 #endif
333 
334 /*
335  * Management Server Interface Command Codes
336  */
337 
338 #define	MS_GTIN		0x0100
339 #define	MS_GIEL		0x0101
340 #define	MS_GIET		0x0111
341 #define	MS_GDID		0x0112
342 #define	MS_GMID		0x0113
343 #define	MS_GFN		0x0114
344 #define	MS_GIELN	0x0115
345 #define	MS_GMAL		0x0116
346 #define	MS_GIEIL	0x0117
347 #define	MS_GPL		0x0118
348 #define	MS_GPT		0x0121
349 #define	MS_GPPN		0x0122
350 #define	MS_GAPNL	0x0124
351 #define	MS_GPS		0x0126
352 #define	MS_GPSC		0x0127
353 #define	MS_GATIN	0x0128
354 #define	MS_GSES		0x0130
355 #define	MS_GPLNL	0x0191
356 #define	MS_GPLT		0x0192
357 #define	MS_GPLML	0x0193
358 #define	MS_GPAB		0x0197
359 #define	MS_GNPL		0x01A1
360 #define	MS_GPNL		0x01A2
361 #define	MS_GPFCP	0x01A4
362 #define	MS_GPLI		0x01A5
363 #define	MS_GNID		0x01B1
364 #define	MS_RIELN	0x0215
365 #define	MS_RPL		0x0280
366 #define	MS_RPLN		0x0291
367 #define	MS_RPLT		0x0292
368 #define	MS_RPLM		0x0293
369 #define	MS_RPAB		0x0298
370 #define	MS_RPFCP	0x029A
371 #define	MS_RPLI		0x029B
372 #define	MS_DPL		0x0380
373 #define	MS_DPLN		0x0391
374 #define	MS_DPLM		0x0392
375 #define	MS_DPLML	0x0393
376 #define	MS_DPLI		0x0394
377 #define	MS_DPAB		0x0395
378 #define	MS_DPALL	0x039F
379 
380 /*
381  * Name Server Command Codes
382  */
383 #define	SLI_CTNS_GA_NXT		0x0100
384 #define	SLI_CTNS_GPN_ID		0x0112
385 #define	SLI_CTNS_GNN_ID		0x0113
386 #define	SLI_CTNS_GCS_ID		0x0114
387 #define	SLI_CTNS_GFT_ID		0x0117
388 #define	SLI_CTNS_GSPN_ID	0x0118
389 #define	SLI_CTNS_GPT_ID		0x011A
390 #define	SLI_CTNS_GID_PN		0x0121
391 #define	SLI_CTNS_GID_NN		0x0131
392 #define	SLI_CTNS_GIP_NN		0x0135
393 #define	SLI_CTNS_GIPA_NN	0x0136
394 #define	SLI_CTNS_GSNN_NN	0x0139
395 #define	SLI_CTNS_GNN_IP		0x0153
396 #define	SLI_CTNS_GIPA_IP	0x0156
397 #define	SLI_CTNS_GID_FT		0x0171
398 #define	SLI_CTNS_GID_PT		0x01A1
399 #define	SLI_CTNS_RPN_ID		0x0212
400 #define	SLI_CTNS_RNN_ID		0x0213
401 #define	SLI_CTNS_RCS_ID		0x0214
402 #define	SLI_CTNS_RFT_ID		0x0217
403 #define	SLI_CTNS_RSPN_ID	0x0218
404 #define	SLI_CTNS_RPT_ID		0x021A
405 #define	SLI_CTNS_RIP_NN		0x0235
406 #define	SLI_CTNS_RIPA_NN	0x0236
407 #define	SLI_CTNS_RSNN_NN	0x0239
408 #define	SLI_CTNS_DA_ID		0x0300
409 
410 #define	SLI_CT_LOOPBACK		0xFCFC
411 
412 
413 /*
414  * Port Types
415  */
416 
417 #define	SLI_CTPT_N_PORT		0x01
418 #define	SLI_CTPT_NL_PORT	0x02
419 #define	SLI_CTPT_FNL_PORT	0x03
420 #define	SLI_CTPT_IP		0x04
421 #define	SLI_CTPT_FCP		0x08
422 #define	SLI_CTPT_NX_PORT	0x7F
423 #define	SLI_CTPT_F_PORT		0x81
424 #define	SLI_CTPT_FL_PORT	0x82
425 #define	SLI_CTPT_E_PORT		0x84
426 
427 #define	SLI_CT_LAST_ENTRY	0x80000000
428 
429 /* ===================================================================== */
430 
431 /*
432  * Start FireFly Register definitions
433  */
434 
435 /* PCI register offsets */
436 #define	MEM_ADDR_OFFSET	0x10	/* SLIM base memory address */
437 #define	MEMH_OFFSET	0x14	/* SLIM base memory high address */
438 #define	REG_ADDR_OFFSET	0x18	/* REGISTER base memory address */
439 #define	REGH_OFFSET	0x1c	/* REGISTER base memory high address */
440 #define	IO_ADDR_OFFSET	0x20	/* BIU I/O registers */
441 #define	REGIOH_OFFSET	0x24	/* REGISTER base io high address */
442 
443 #define	CMD_REG_OFFSET	0x4	/* PCI command configuration */
444 
445 /* General PCI Register Definitions */
446 /* Refer To The PCI Specification For Detailed Explanations */
447 
448 #define	PCI_VENDOR_ID_REGISTER		0x00	/* PCI Vendor ID Reg */
449 #define	PCI_DEVICE_ID_REGISTER		0x02	/* PCI Device ID Reg */
450 #define	PCI_CONFIG_ID_REGISTER		0x00	/* PCI Configuration ID Reg */
451 #define	PCI_COMMAND_REGISTER		0x04	/* PCI Command Reg */
452 #define	PCI_STATUS_REGISTER		0x06	/* PCI Status Reg */
453 #define	PCI_REV_ID_REGISTER		0x08	/* PCI Revision ID Reg */
454 #define	PCI_CLASS_CODE_REGISTER		0x09	/* PCI Class Code Reg */
455 #define	PCI_CACHE_LINE_REGISTER		0x0C	/* PCI Cache Line Reg */
456 #define	PCI_LATENCY_TMR_REGISTER	0x0D	/* PCI Latency Timer Reg */
457 #define	PCI_HEADER_TYPE_REGISTER	0x0E	/* PCI Header Type Reg */
458 #define	PCI_BIST_REGISTER		0x0F	/* PCI Built-In SelfTest Reg */
459 #define	PCI_BAR_0_REGISTER		0x10	/* PCI Base Address Reg 0 */
460 #define	PCI_BAR_1_REGISTER		0x14	/* PCI Base Address Reg 1 */
461 #define	PCI_BAR_2_REGISTER		0x18	/* PCI Base Address Reg 2 */
462 #define	PCI_BAR_3_REGISTER		0x1C	/* PCI Base Address Reg 3 */
463 #define	PCI_BAR_4_REGISTER		0x20	/* PCI Base Address Reg 4 */
464 #define	PCI_BAR_5_REGISTER		0x24	/* PCI Base Address Reg 5 */
465 #define	PCI_SSID_REGISTER		0x2C
466 #define	PCI_SSVID_REGISTER		0x2C
467 #define	PCI_SSDID_REGISTER		0x2E
468 #define	PCI_EXPANSION_ROM		0x30	/* PCI Expansion ROM Base Reg */
469 #define	PCI_CAP_POINTER			0x34
470 
471 /* PCI capatability registers are defined in pci.h */
472 #define	PCI_CAP_ID_SHIFT			0
473 #define	PCI_CAP_ID_MASK				0xff
474 #define	PCI_CAP_NEXT_PTR_SHIFT			8
475 #define	PCI_CAP_NEXT_PTR_MASK			0xff
476 
477 /* PCI extended capatability registers are defined in pcie.h */
478 #define	PCI_EXT_CAP_MAX_PTR		0x30
479 
480 #define	PCI_EXT_CAP_ID_MRIOV		0x0000 /* ??? */
481 #define	PCI_EXT_CAP_ID_SRIOV		0x0010
482 #define	PCI_EXT_CAP_ID_11		0x0011
483 #define	PCI_EXT_CAP_ID_12		0x0012
484 #define	PCI_EXT_CAP_ID_13		0x0013
485 #define	PCI_EXT_CAP_ID_14		0x0014
486 #define	PCI_EXT_CAP_ID_15		0x0015
487 #define	PCI_EXT_CAP_ID_16		0x0016
488 #define	PCI_EXT_CAP_ID_TPH		0x0017
489 #define	PCI_EXT_CAP_ID_18		0x0018
490 #define	PCI_EXT_CAP_ID_SEC_PCI		0x0019
491 
492 /* Vendor Specific (VS) register */
493 #define	PCI_VS_SLI_INTF_OFFSET	4
494 
495 /* PCI access methods */
496 #define	P_CONF_T1	1
497 #define	P_CONF_T2	2
498 
499 /* max number of pci buses */
500 #define	MAX_PCI_BUSES	0xFF
501 
502 /* number of PCI config bytes to access */
503 #define	PCI_BYTE	1
504 #define	PCI_WORD	2
505 #define	PCI_DWORD	4
506 
507 /* PCI related constants */
508 #define	CMD_IO_ENBL	0x0001
509 #define	CMD_MEM_ENBL	0x0002
510 #define	CMD_BUS_MASTER	0x0004
511 #define	CMD_MWI		0x0010
512 #define	CMD_PARITY_CHK	0x0040
513 #define	CMD_SERR_ENBL	0x0100
514 
515 #define	CMD_CFG_VALUE	0x156	/* mem enable, master, MWI, SERR, PERR */
516 
517 /* PCI addresses */
518 #define	PCI_SPACE_ENABLE		0x0CF8
519 #define	CF1_CONFIG_ADDR_REGISTER	0x0CF8
520 #define	CF1_CONFIG_DATA_REGISTER	0x0CFC
521 #define	CF2_FORWARD_REGISTER		0x0CFA
522 #define	CF2_BASE_ADDRESS		0xC000
523 
524 
525 #define	DEFAULT_PCI_LATENCY_CLOCKS	0xf8	/* 0xF8 is a special value */
526 						/* for FF11.1N6 firmware. */
527 						/* Use 0x80 for pre-FF11.1N6 */
528 						/* &N7, etc */
529 #define	PCI_LATENCY_VALUE		0xf8
530 
531 
532 
533 /* ==== Register Bit Definitions ==== */
534 
535 /* Used by SBUS adapter */
536 /* SBUS Control Register */
537 #define	SBUS_CTRL_REG_OFFSET	0	/* Word offset from reg base addr */
538 
539 #define	SBUS_CTRL_SBRST 	0x00000001	/* Bit  0 */
540 #define	SBUS_CTRL_BKOFF 	0x00000002	/* Bit  1 */
541 #define	SBUS_CTRL_ENP 		0x00000004	/* Bit  2 */
542 #define	SBUS_CTRL_EN64		0x00000008	/* Bit  3 */
543 #define	SBUS_CTRL_SIR_1 	0x00000010	/* Bit [6:4] IRL 1, */
544 						/* lowset priority */
545 #define	SBUS_CTRL_SIR_2 	0x00000020
546 #define	SBUS_CTRL_SIR_3 	0x00000030
547 #define	SBUS_CTRL_SIR_4 	0x00000040
548 #define	SBUS_CTRL_SIR_5 	0x00000050
549 #define	SBUS_CTRL_SIR_6 	0x00000060
550 #define	SBUS_CTRL_SIR_7 	0x00000070	/* IRL 7, highest priority */
551 
552 /* SBUS Status Register */
553 #define	SBUS_STAT_REG_OFFSET	1	/* Word offset from reg base addr */
554 #define	SBUS_STAT_IP		0x00000001	/* Bit  0 */
555 #define	SBUS_STAT_LERR		0x00000002	/* Bit  1 */
556 #define	SBUS_STAT_SBPE		0x00000004	/* Bit  2 */
557 #define	SBUS_STAT_TE		0x00000008	/* Bit  3 */
558 #define	SBUS_STAT_WPE		0x00000010	/* Bit  4 */
559 #define	SBUS_STAT_PERR		0x00000020	/* Bit  5 */
560 #define	SBUS_STAT_SERR		0x00000040	/* Bit  6 */
561 #define	SBUS_STAT_PTA		0x00000080	/* Bit  7 */
562 
563 /* SBUS Update Register */
564 #define	SBUS_UPDATE_REG_OFFSET	2	/* Word offfset from reg base addr */
565 
566 #define	SBUS_UPDATE_DATA	0x00000001	/* Bit  0 */
567 #define	SBUS_UPDATE_SPCLK	0x00000002	/* Bit  1 */
568 #define	SBUS_UPDATE_SPCE	0x00000004	/* Bit  2 */
569 #define	SBUS_UPDATE_SPRST	0x00000008	/* Bit  3 */
570 #define	SBUS_UPDATE_SPWE	0x00000010	/* Bit  4 */
571 #define	SBUS_UPDATE_LDFPGA	0x00000080	/* Bit  7 */
572 
573 /* Host Attention Register */
574 
575 #define	HA_REG_OFFSET  0	/* Word offset from register base address */
576 
577 #define	HA_R0RE_REQ	0x00000001	/* Bit  0 */
578 #define	HA_R0CE_RSP	0x00000002	/* Bit  1 */
579 #define	HA_R0ATT	0x00000008	/* Bit  3 */
580 #define	HA_R1RE_REQ	0x00000010	/* Bit  4 */
581 #define	HA_R1CE_RSP	0x00000020	/* Bit  5 */
582 #define	HA_R1ATT	0x00000080	/* Bit  7 */
583 #define	HA_R2RE_REQ	0x00000100	/* Bit  8 */
584 #define	HA_R2CE_RSP	0x00000200	/* Bit  9 */
585 #define	HA_R2ATT	0x00000800	/* Bit 11 */
586 #define	HA_R3RE_REQ	0x00001000	/* Bit 12 */
587 #define	HA_R3CE_RSP	0x00002000	/* Bit 13 */
588 #define	HA_R3ATT	0x00008000	/* Bit 15 */
589 #define	HA_LATT		0x20000000	/* Bit 29 */
590 #define	HA_MBATT	0x40000000	/* Bit 30 */
591 #define	HA_ERATT	0x80000000	/* Bit 31 */
592 
593 
594 #ifdef MSI_SUPPORT
595 
596 
597 /* Host attention interrupt map */
598 #define	EMLXS_MSI_MAP8	{0, HA_R0ATT, HA_R1ATT, HA_R2ATT, \
599 	HA_R3ATT, HA_LATT, HA_MBATT, HA_ERATT}
600 #define	EMLXS_MSI_MAP4	{0, HA_R0ATT, HA_R1ATT, HA_R2ATT, 0, 0, 0, 0}
601 #define	EMLXS_MSI_MAP2	{0, HA_R0ATT, 0, 0, 0, 0, 0, 0}
602 #define	EMLXS_MSI_MAP1	{0, 0, 0, 0, 0, 0, 0, 0}
603 
604 /* MSI 0 interrupt mask */
605 #define	EMLXS_MSI0_MASK8	0
606 #define	EMLXS_MSI0_MASK4	(HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \
607 				HC_ERINT_ENA)
608 #define	EMLXS_MSI0_MASK2	(HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \
609 				HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA)
610 #define	EMLXS_MSI0_MASK1	(HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA| \
611 				HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \
612 				HC_ERINT_ENA)
613 
614 
615 #define	EMLXS_MSI_MAX_INTRS	8
616 
617 #define	EMLXS_MSI_MODE1		0
618 #define	EMLXS_MSI_MODE2		1
619 #define	EMLXS_MSI_MODE4		2
620 #define	EMLXS_MSI_MODE8		3
621 #define	EMLXS_MSI_MODES		4
622 
623 #endif	/* MSI_SUPPORT */
624 
625 
626 #define	IO_THROTTLE_RESERVE	12
627 
628 
629 
630 
631 /* Chip Attention Register */
632 
633 #define	CA_REG_OFFSET	1	/* Word offset from register base address */
634 
635 #define	CA_R0CE_REQ	0x00000001	/* Bit  0 */
636 #define	CA_R0RE_RSP	0x00000002	/* Bit  1 */
637 #define	CA_R0ATT	0x00000008	/* Bit  3 */
638 #define	CA_R1CE_REQ	0x00000010	/* Bit  4 */
639 #define	CA_R1RE_RSP	0x00000020	/* Bit  5 */
640 #define	CA_R1ATT	0x00000080	/* Bit  7 */
641 #define	CA_R2CE_REQ	0x00000100	/* Bit  8 */
642 #define	CA_R2RE_RSP	0x00000200	/* Bit  9 */
643 #define	CA_R2ATT	0x00000800	/* Bit 11 */
644 #define	CA_R3CE_REQ	0x00001000	/* Bit 12 */
645 #define	CA_R3RE_RSP	0x00002000	/* Bit 13 */
646 #define	CA_R3ATT	0x00008000	/* Bit 15 */
647 #define	CA_MBATT	0x40000000	/* Bit 30 */
648 
649 /* Host Status Register */
650 
651 #define	HS_REG_OFFSET	2	/* Word offset from register base address */
652 
653 #define	HS_OVERTEMP	0x00000100	/* Bit 8 */
654 #define	HS_MBRDY	0x00400000	/* Bit 22 */
655 #define	HS_FFRDY	0x00800000	/* Bit 23 */
656 #define	HS_FFER8	0x01000000	/* Bit 24 */
657 #define	HS_FFER7	0x02000000	/* Bit 25 */
658 #define	HS_FFER6	0x04000000	/* Bit 26 */
659 #define	HS_FFER5	0x08000000	/* Bit 27 */
660 #define	HS_FFER4	0x10000000	/* Bit 28 */
661 #define	HS_FFER3	0x20000000	/* Bit 29 */
662 #define	HS_FFER2	0x40000000	/* Bit 30 */
663 #define	HS_FFER1	0x80000000	/* Bit 31 */
664 #define	HS_FFERM	0xFF000000	/* Mask for error bits 31:24 */
665 
666 /* Host Control Register */
667 
668 #define	HC_REG_OFFSET	3	/* Word offset from register base address */
669 
670 #define	HC_MBINT_ENA	0x00000001	/* Bit  0 */
671 #define	HC_R0INT_ENA	0x00000002	/* Bit  1 */
672 #define	HC_R1INT_ENA	0x00000004	/* Bit  2 */
673 #define	HC_R2INT_ENA	0x00000008	/* Bit  3 */
674 #define	HC_R3INT_ENA	0x00000010	/* Bit  4 */
675 #define	HC_INITHBI	0x02000000	/* Bit 25 */
676 #define	HC_INITMB	0x04000000	/* Bit 26 */
677 #define	HC_INITFF	0x08000000	/* Bit 27 */
678 #define	HC_LAINT_ENA	0x20000000	/* Bit 29 */
679 #define	HC_ERINT_ENA	0x80000000	/* Bit 31 */
680 
681 /* BIU Configuration Register */
682 
683 #define	BC_REG_OFFSET	4	/* Word offset from register base address */
684 
685 #define	BC_BSE		0x00000001	/* Bit 0 */
686 #define	BC_BSE_SWAP	0x01000000	/* Bit 0 - swapped */
687 
688 /*
689  * End FireFly Register definitions
690  */
691 
692 /*
693  * Start SLI 4 section.
694  */
695 
696 /* PCI Config Register offsets */
697 #define	PCICFG_UE_STATUS_LO_OFFSET	0xA0	/* Error Indication - low */
698 #define	PCICFG_UE_STATUS_HI_OFFSET	0xA4	/* Error Indication - high */
699 #define	PCICFG_UE_MASK_LO_OFFSET	0xA8	/* Error mask - low */
700 #define	PCICFG_UE_MASK_HI_OFFSET	0xAC	/* Error mask - high */
701 #define	PCICFG_UE_STATUS_ONLINE1	0xB0	/* Error status1 */
702 #define	PCICFG_UE_STATUS_ONLINE2	0xB4	/* Error status2 */
703 
704 /* BAR1 and BAR2 register offsets */
705 
706 /* BAR1 offsets for principal registers */
707 #define	CSR_ISR0_OFFSET		0x0C18	/* CSR for EQ interrupt indications */
708 #define	CSR_IMR0_OFFSET		0x0C48	/* CSR for EQ interrupt masking */
709 #define	CSR_ISCR0_OFFSET	0x0C78	/* CSR for EQ interrupt clearing */
710 
711 #define	ISR0_EQ0_INDC	0x00000001	/* Indication bit for EQ0 */
712 #define	ISR0_EQ1_INDC	0x00000002	/* Indication bit for EQ1 */
713 #define	ISR0_EQ2_INDC	0x00000004	/* Indication bit for EQ2 */
714 #define	ISR0_EQ3_INDC	0x00000008	/* Indication bit for EQ3 */
715 #define	ISR0_EQ4_INDC	0x00000010	/* Indication bit for EQ4 */
716 #define	ISR0_EQ5_INDC	0x00000020	/* Indication bit for EQ5 */
717 #define	ISR0_EQ6_INDC	0x00000040	/* Indication bit for EQ6 */
718 #define	ISR0_EQ7_INDC	0x00000080	/* Indication bit for EQ7 */
719 
720 /* MPU EP Semaphore register (ARM POST) */
721 #define	CSR_MPU_EP_SEMAPHORE_OFFSET	0x00AC
722 
723 /* SLI Status register */
724 #define	SLI_STATUS_ERROR		0x80000000
725 #define	SLI_STATUS_BE			0x40000000
726 #define	SLI_STATUS_OTI			0x20000000
727 #define	SLI_STATUS_DUMP_LOCATION	0x04000000
728 #define	SLI_STATUS_DUMP_IMAGE_PRESENT	0x02000000
729 #define	SLI_STATUS_RESET_NEEDED		0x01000000
730 #define	SLI_STATUS_READY		0x00800000
731 #define	SLI_STATUS_INTERRUPT_DISABLE	0x00400000
732 
733 /* SLI Control register */
734 #define	SLI_CNTL_BE		0x40000000
735 #define	SLI_CNTL_INIT_PORT	0x08000000
736 
737 /* SLI PHYDEV Control register */
738 #define	SLI_PHYDEV_RERROR	0x80000000
739 #define	SLI_PHYDEV_INP		0x40000000
740 #define	SLI_PHYDEV_IPLD		0x00008000
741 #define	SLI_PHYDEV_GPC		0x00004000
742 #define	SLI_PHYDEV_GP		0x00002000
743 
744 #define	SLI_PHYDEV_RC_MASK	0x00000700
745 #define	SLI_PHYDEV_RC_UNKNOWN	0x00000000
746 #define	SLI_PHYDEV_RC_PROFILE	0x00000100
747 #define	SLI_PHYDEV_RC_FACTORY	0x00000200
748 
749 #define	SLI_PHYDEV_FRL_MASK	0x000000F0
750 #define	SLI_PHYDEV_FRL_ALL	0x00000000
751 #define	SLI_PHYDEV_FRL_FCOE	0x00000010
752 
753 #define	SLI_PHYDEV_LC		0x00000008
754 #define	SLI_PHYDEV_DD		0x00000004
755 #define	SLI_PHYDEV_FRST		0x00000002
756 #define	SLI_PHYDEV_DRST		0x00000001
757 
758 /* POST Stages of interest */
759 #define	ARM_POST_FATAL	0x80000000
760 #define	ARM_POST_READY	0xc000
761 #define	ARM_POST_MASK	0xffff
762 #define	ARM_UNRECOVERABLE_ERROR	0xf000
763 
764 #define	MPU_EP_DL	0x04000000	/* Driverloadedbitmask */
765 #define	MPU_EP_ORI	0x08000000	/* OptionROMinstalledbitmask */
766 #define	MPU_EP_IPC	0x10000000	/* IPaddressconflictmask */
767 #define	MPU_EP_NIP	0x20000000	/* NoIPaddressmask */
768 #define	MPU_EP_BFW	0x40000000	/* BackupFWinusemask */
769 #define	MPU_EP_ERR	0x80000000	/* POSTfatalerrormask */
770 
771 /* BAR2 offsets for principal doorbell registers */
772 
773 #define	PD_RQ_DB_OFFSET	0x00A0	/* Doorbell notify of posted RQEs */
774 #define	PD_WQ_DB_OFFSET	0x0040	/* Doorbell notify of posted WQEs */
775 #define	PD_CQ_DB_OFFSET	0x0120	/* Doorbell notify of processed CQEs or EQEs */
776 #define	PD_MQ_DB_OFFSET	0x0140	/* Doorbell notify of posted MQEs */
777 #define	PD_MB_DB_OFFSET	0x0160	/* Doorbell Bootstrap Mailbox */
778 
779 #define	SLIPORT_SEMAPHORE_OFFSET	0x0400
780 #define	SLIPORT_STATUS_OFFSET		0x0404
781 #define	SLIPORT_CONTROL_OFFSET		0x0408
782 #define	SLIPORT_ERROR1_OFFSET		0x040C
783 #define	SLIPORT_ERROR2_OFFSET		0x0410
784 #define	PHYSDEV_CONTROL_OFFSET		0x0414
785 
786 
787 /* Doorbell definitions */
788 
789 /* Defines for MQ doorbell */
790 #define	MQ_DB_POP_SHIFT 16		/* shift for entries popped */
791 #define	MQ_DB_POP_MASK  0x1FFF0000	/* Mask for number of entries popped */
792 
793 /* Defines for CQ doorbell */
794 #define	CQ_DB_POP_SHIFT 16		/* shift for entries popped */
795 #define	CQ_DB_POP_MASK  0x1FFF0000	/* Mask for number of entries popped */
796 #define	CQ_DB_REARM	0x20000000	/* Bit 29, rearm */
797 
798 /* Defines for EQ doorbell */
799 #define	EQ_DB_CLEAR	0x00000200	/* Bit 9, designates clear EQ ISR */
800 #define	EQ_DB_EVENT	0x00000400	/* Bit 10, designates EQ */
801 #define	EQ_DB_POP_SHIFT 16		/* shift for entries popped */
802 #define	EQ_DB_POP_MASK  0x1FFF0000	/* Mask for number of entries popped */
803 #define	EQ_DB_REARM	0x20000000	/* Bit 29, rearm */
804 
805 /* bootstrap mailbox doorbell defines */
806 #define	BMBX_READY	0x00000001	/* Mask for Port Ready bit */
807 #define	BMBX_ADDR_HI	0x00000002	/* Mask for Addr Hi bit */
808 #define	BMBX_ADDR	0xFFFFFFFA	/* Mask for Addr bits */
809 
810 /* Sizeof bootstrap mailbox */
811 #define	EMLXS_BOOTSTRAP_MB_SIZE	256
812 
813 #define	FW_INITIALIZE_WORD0	0xFF1234FF /* Initialize bootstrap wd 0 */
814 #define	FW_INITIALIZE_WORD1	0xFF5678FF /* Initialize bootstrap wd 1 */
815 
816 #define	FW_DEINITIALIZE_WORD0	0xFFAABBFF /* DeInitialize bootstrap wd 0 */
817 #define	FW_DEINITIALIZE_WORD1	0xFFCCDDFF /* DeInitialize bootstrap wd 1 */
818 
819 /* ===================================================================== */
820 
821 /*
822  * Start of FCP specific structures
823  */
824 
825 typedef struct emlxs_fcp_rsp
826 {
827 	uint32_t	rspRsvd1;	/* FC Word 0, byte 0:3 */
828 	uint32_t	rspRsvd2;	/* FC Word 1, byte 0:3 */
829 
830 	uint8_t		rspStatus0;	/* FCP_STATUS byte 0 (reserved) */
831 	uint8_t		rspStatus1;	/* FCP_STATUS byte 1 (reserved) */
832 	uint8_t		rspStatus2;	/* FCP_STATUS byte 2 field validity */
833 #define	RSP_LEN_VALID	0x01	/* bit 0 */
834 #define	SNS_LEN_VALID	0x02	/* bit 1 */
835 #define	RESID_OVER	0x04	/* bit 2 */
836 #define	RESID_UNDER	0x08	/* bit 3 */
837 
838 	uint8_t		rspStatus3;	/* FCP_STATUS byte 3 SCSI status byte */
839 #define	SCSI_STAT_GOOD		0x00
840 #define	SCSI_STAT_CHECK_COND	0x02
841 #define	SCSI_STAT_COND_MET	0x04
842 #define	SCSI_STAT_BUSY		0x08
843 #define	SCSI_STAT_INTERMED	0x10
844 #define	SCSI_STAT_INTERMED_CM	0x14
845 #define	SCSI_STAT_RES_CNFLCT	0x18
846 #define	SCSI_STAT_CMD_TERM	0x22
847 #define	SCSI_STAT_QUE_FULL	0x28
848 #define	SCSI_STAT_ACA_ACTIVE	0x30
849 #define	SCSI_STAT_TASK_ABORT	0x40
850 
851 	uint32_t	rspResId;	/* Residual xfer if RESID_xxxx set */
852 					/* in fcpStatus2. */
853 					/* Received in Big Endian format */
854 	uint32_t	rspSnsLen;	/* Length of sense data in fcpSnsInfo */
855 					/* Received in Big Endian format */
856 	uint32_t	rspRspLen;	/* Length of FCP response data */
857 					/* in fcpRspInfo */
858 					/* Received in Big Endian format */
859 
860 	uint8_t		rspInfo0;	/* FCP_RSP_INFO byte 0 (reserved) */
861 	uint8_t		rspInfo1;	/* FCP_RSP_INFO byte 1 (reserved) */
862 	uint8_t		rspInfo2;	/* FCP_RSP_INFO byte 2 (reserved) */
863 	uint8_t		rspInfo3;	/* FCP_RSP_INFO RSP_CODE byte 3 */
864 
865 #define	RSP_NO_FAILURE		0x00
866 #define	RSP_DATA_BURST_ERR	0x01
867 #define	RSP_CMD_FIELD_ERR	0x02
868 #define	RSP_RO_MISMATCH_ERR	0x03
869 #define	RSP_TM_NOT_SUPPORTED	0x04	/* Task mgmt function not supported */
870 #define	RSP_TM_NOT_COMPLETED	0x05	/* Task mgmt function not performed */
871 
872 	uint32_t	rspInfoRsvd;	/* FCP_RSP_INFO bytes 4-7 (reserved) */
873 
874 	/*
875 	 * Define maximum size of SCSI Sense buffer.
876 	 * Seagate never issues more than 18 bytes of Sense data
877 	 */
878 #define	MAX_FCP_SNS	128
879 	uint8_t		rspSnsInfo[MAX_FCP_SNS];
880 } emlxs_fcp_rsp;
881 typedef emlxs_fcp_rsp FCP_RSP;
882 
883 
884 typedef struct emlxs_fcp_cmd
885 {
886 	uint32_t	fcpLunMsl;	/* most significant lun word */
887 	uint32_t	fcpLunLsl;	/* least significant lun word */
888 
889 	/*
890 	 * # of bits to shift lun id to end up in right payload word,
891 	 * little endian = 8, big = 16.
892 	 */
893 #ifdef EMLXS_LITTLE_ENDIAN
894 #define	FC_LUN_SHIFT		8
895 #define	FC_ADDR_MODE_SHIFT	0
896 #endif
897 #ifdef EMLXS_BIG_ENDIAN
898 #define	FC_LUN_SHIFT		16
899 #define	FC_ADDR_MODE_SHIFT	24
900 #endif
901 
902 	uint8_t		fcpCntl0;	/* FCP_CNTL byte 0 (reserved) */
903 	uint8_t		fcpCntl1;	/* FCP_CNTL byte 1 task codes */
904 #define	SIMPLE_Q	0x00
905 #define	HEAD_OF_Q	0x01
906 #define	ORDERED_Q	0x02
907 #define	ACA_Q		0x04
908 #define	UNTAGGED	0x05
909 
910 	uint8_t		fcpCntl2;	/* FCP_CTL byte 2 task management */
911 					/* codes */
912 #define	ABORT_TASK_SET	0x02	/* Bit 1 */
913 #define	CLEAR_TASK_SET	0x04	/* bit 2 */
914 #define	LUN_RESET	0x10	/* bit 4 */
915 #define	TARGET_RESET	0x20	/* bit 5 */
916 #define	CLEAR_ACA	0x40	/* bit 6 */
917 #define	TERMINATE_TASK	0x80	/* bit 7 */
918 
919 	uint8_t		fcpCntl3;
920 #define	WRITE_DATA	0x01	/* Bit 0 */
921 #define	READ_DATA	0x02	/* Bit 1 */
922 
923 	uint8_t		fcpCdb[16];	/* SRB cdb field is copied here */
924 	uint32_t	fcpDl;	/* Total transfer length */
925 } emlxs_fcp_cmd_t;
926 typedef emlxs_fcp_cmd_t FCP_CMND;
927 
928 
929 
930 
931 /* SCSI INQUIRY Command Structure */
932 
933 typedef struct emlxs_inquiryDataType
934 {
935 	uint8_t		DeviceType:5;
936 	uint8_t		DeviceTypeQualifier:3;
937 
938 	uint8_t		DeviceTypeModifier:7;
939 	uint8_t		RemovableMedia:1;
940 
941 	uint8_t		Versions;
942 	uint8_t		ResponseDataFormat;
943 	uint8_t		AdditionalLength;
944 	uint8_t		Reserved[2];
945 
946 	uint8_t		SoftReset:1;
947 	uint8_t		CommandQueue:1;
948 	uint8_t		Reserved2:1;
949 	uint8_t		LinkedCommands:1;
950 	uint8_t		Synchronous:1;
951 	uint8_t		Wide16Bit:1;
952 	uint8_t		Wide32Bit:1;
953 	uint8_t		RelativeAddressing:1;
954 
955 	uint8_t		VendorId[8];
956 	uint8_t		ProductId[16];
957 	uint8_t		ProductRevisionLevel[4];
958 	uint8_t		VendorSpecific[20];
959 	uint8_t		Reserved3[40];
960 } emlxs_inquiry_data_type_t;
961 typedef emlxs_inquiry_data_type_t INQUIRY_DATA_DEF;
962 
963 
964 typedef struct emlxs_read_capacity_data
965 {
966 	uint32_t	LogicalBlockAddress;
967 	uint32_t	BytesPerBlock;
968 } emlxs_read_capacity_data_t;
969 typedef emlxs_read_capacity_data_t READ_CAPACITY_DATA_DEF;
970 
971 
972 /* SCSI CDB command codes */
973 #define	FCP_SCSI_FORMAT_UNIT			0x04
974 #define	FCP_SCSI_INQUIRY			0x12
975 #define	FCP_SCSI_MODE_SELECT			0x15
976 #define	FCP_SCSI_MODE_SENSE			0x1A
977 #define	FCP_SCSI_PAUSE_RESUME			0x4B
978 #define	FCP_SCSI_PLAY_AUDIO			0x45
979 #define	FCP_SCSI_PLAY_AUDIO_EXT			0xA5
980 #define	FCP_SCSI_PLAY_AUDIO_MSF			0x47
981 #define	FCP_SCSI_PLAY_AUDIO_TRK_INDX		0x48
982 #define	FCP_SCSI_PREVENT_ALLOW_REMOVAL		0x1E
983 #define	FCP_SCSI_READ_CMD			0x08
984 #define	FCP_SCSI_READ_BUFFER			0x3C
985 #define	FCP_SCSI_READ_CAPACITY			0x25
986 #define	FCP_SCSI_READ_DEFECT_LIST		0x37
987 #define	FCP_SCSI_READ_EXTENDED			0x28
988 #define	FCP_SCSI_READ_HEADER			0x44
989 #define	FCP_SCSI_READ_LONG			0xE8
990 #define	FCP_SCSI_READ_SUB_CHANNEL		0x42
991 #define	FCP_SCSI_READ_TOC			0x43
992 #define	FCP_SCSI_REASSIGN_BLOCK			0x07
993 #define	FCP_SCSI_RECEIVE_DIAGNOSTIC_RESULTS	0x1C
994 #define	FCP_SCSI_RELEASE_UNIT			0x17
995 #define	FCP_SCSI_REPORT_LUNS			0xa0
996 #define	FCP_SCSI_REQUEST_SENSE			0x03
997 #define	FCP_SCSI_RESERVE_UNIT			0x16
998 #define	FCP_SCSI_REZERO_UNIT			0x01
999 #define	FCP_SCSI_SEEK				0x0B
1000 #define	FCP_SCSI_SEEK_EXTENDED			0x2B
1001 #define	FCP_SCSI_SEND_DIAGNOSTIC		0x1D
1002 #define	FCP_SCSI_START_STOP_UNIT		0x1B
1003 #define	FCP_SCSI_TEST_UNIT_READY		0x00
1004 #define	FCP_SCSI_VERIFY				0x2F
1005 #define	FCP_SCSI_WRITE_CMD			0x0A
1006 #define	FCP_SCSI_WRITE_AND_VERIFY		0x2E
1007 #define	FCP_SCSI_WRITE_BUFFER			0x3B
1008 #define	FCP_SCSI_WRITE_EXTENDED			0x2A
1009 #define	FCP_SCSI_WRITE_LONG			0xEA
1010 #define	FCP_SCSI_RELEASE_LUNR			0xBB
1011 #define	FCP_SCSI_RELEASE_LUNV			0xBF
1012 
1013 #define	HPVA_SETPASSTHROUGHMODE			0x27
1014 #define	HPVA_EXECUTEPASSTHROUGH			0x29
1015 #define	HPVA_CREATELUN				0xE2
1016 #define	HPVA_SETLUNSECURITYLIST			0xED
1017 #define	HPVA_SETCLOCK				0xF9
1018 #define	HPVA_RECOVER				0xFA
1019 #define	HPVA_GENERICSERVICEOUT			0xFD
1020 
1021 #define	DMEP_EXPORT_IN				0x85
1022 #define	DMEP_EXPORT_OUT				0x89
1023 
1024 #define	MDACIOCTL_DIRECT_CMD			0x22
1025 #define	MDACIOCTL_STOREIMAGE			0x2C
1026 #define	MDACIOCTL_WRITESIGNATURE		0xA6
1027 #define	MDACIOCTL_SETREALTIMECLOCK		0xAC
1028 #define	MDACIOCTL_PASS_THRU_CDB			0xAD
1029 #define	MDACIOCTL_PASS_THRU_INITIATE		0xAE
1030 #define	MDACIOCTL_CREATENEWCONF			0xC0
1031 #define	MDACIOCTL_ADDNEWCONF			0xC4
1032 #define	MDACIOCTL_MORE				0xC6
1033 #define	MDACIOCTL_SETPHYSDEVPARAMETER		0xC8
1034 #define	MDACIOCTL_SETLOGDEVPARAMETER		0xCF
1035 #define	MDACIOCTL_SETCONTROLLERPARAMETER	0xD1
1036 #define	MDACIOCTL_WRITESANMAP			0xD4
1037 #define	MDACIOCTL_SETMACADDRESS			0xD5
1038 
1039 /*
1040  * End of FCP specific structures
1041  */
1042 
1043 #define	FL_ALPA		0x00	/* AL_PA of FL_Port */
1044 
1045 /* Fibre Channel Service Parameter definitions */
1046 
1047 #define	FC_PH_4_0	6	/* FC-PH version 4.0 */
1048 #define	FC_PH_4_1	7	/* FC-PH version 4.1 */
1049 #define	FC_PH_4_2	8	/* FC-PH version 4.2 */
1050 #define	FC_PH_4_3	9	/* FC-PH version 4.3 */
1051 
1052 #define	FC_PH_LOW	8	/* Lowest supported FC-PH version */
1053 #define	FC_PH_HIGH	9	/* Highest supported FC-PH version */
1054 #define	FC_PH3		0x20	/* FC-PH-3 version */
1055 
1056 #define	FF_FRAME_SIZE	2048
1057 
1058 
1059 typedef struct emlxs_rings
1060 {
1061 #ifdef EMLXS_BIG_ENDIAN
1062 	uint32_t	crReserved:16;
1063 	uint32_t	crBegin:8;
1064 	uint32_t	crEnd:8;	/* Low order bit first word */
1065 	uint32_t	rrReserved:16;
1066 	uint32_t	rrBegin:8;
1067 	uint32_t	rrEnd:8;	/* Low order bit second word */
1068 #endif
1069 #ifdef EMLXS_LITTLE_ENDIAN
1070 	uint32_t	crEnd:8;	/* Low order bit first word */
1071 	uint32_t	crBegin:8;
1072 	uint32_t	crReserved:16;
1073 	uint32_t	rrEnd:8;	/* Low order bit second word */
1074 	uint32_t	rrBegin:8;
1075 	uint32_t	rrReserved:16;
1076 #endif
1077 } emlxs_rings_t;
1078 typedef emlxs_rings_t RINGS;
1079 
1080 
1081 typedef struct emlxs_ring_def
1082 {
1083 #ifdef EMLXS_BIG_ENDIAN
1084 	uint16_t	offCiocb;
1085 	uint16_t	numCiocb;
1086 	uint16_t	offRiocb;
1087 	uint16_t	numRiocb;
1088 #endif
1089 #ifdef EMLXS_LITTLE_ENDIAN
1090 	uint16_t	numCiocb;
1091 	uint16_t	offCiocb;
1092 	uint16_t	numRiocb;
1093 	uint16_t	offRiocb;
1094 #endif
1095 } emlxs_ring_def_t;
1096 typedef emlxs_ring_def_t RING_DEF;
1097 
1098 /*
1099  * The following F.C. frame stuctures are defined in Big Endian format.
1100  */
1101 
1102 typedef struct emlxs_name_type
1103 {
1104 #ifdef EMLXS_BIG_ENDIAN
1105 	uint8_t		nameType:4;	/* FC Word 0, bit 28:31 */
1106 	uint8_t		IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit 8:11 */
1107 					/* of IEEE ext */
1108 #endif
1109 #ifdef EMLXS_LITTLE_ENDIAN
1110 	uint8_t		IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit 8:11 */
1111 					/* of IEEE ext */
1112 	uint8_t		nameType:4;	/* FC Word 0, bit 28:31 */
1113 #endif
1114 #define	NAME_IEEE		0x1	/* IEEE name - nameType */
1115 #define	NAME_IEEE_EXT		0x2	/* IEEE extended name */
1116 #define	NAME_FC_TYPE		0x3	/* FC native name type */
1117 #define	NAME_IP_TYPE		0x4	/* IP address */
1118 #define	NAME_CCITT_TYPE		0xC
1119 #define	NAME_CCITT_GR_TYPE	0xE
1120 	uint8_t		IEEEextLsb;	/* FC Word 0, bit 16:23, */
1121 					/* IEEE extended Lsb */
1122 	uint8_t		IEEE[6];	/* FC IEEE address */
1123 } emlxs_name_type_t;
1124 typedef emlxs_name_type_t NAME_TYPE;
1125 
1126 
1127 /*
1128  * Word 1 Bit 31 in common service parameter is overloaded.
1129  * Word 1 Bit 31 in FLOGI/FDISC request is multiple NPort request
1130  * Word 1 Bit 31 in FLOGI/FDISC response is clean address bit
1131  */
1132 #define	CLEAN_ADDRESS_BIT reqMultipleNPort /* Word 1, bit 31 */
1133 
1134 typedef struct emlxs_csp
1135 {
1136 	uint8_t		fcphHigh;		/* FC Word 0, byte 0 */
1137 	uint8_t		fcphLow;
1138 	uint8_t		bbCreditMsb;
1139 	uint8_t		bbCreditlsb;		/* FC Word 0, byte 3 */
1140 #ifdef EMLXS_BIG_ENDIAN
1141 	uint16_t	reqMultipleNPort:1;	/* FC Word 1, bit 31 */
1142 	uint16_t	randomOffset:1;		/* FC Word 1, bit 30 */
1143 	uint16_t	rspMultipleNPort:1;	/* FC Word 1, bit 29 */
1144 	uint16_t	fPort:1;		/* FC Word 1, bit 28 */
1145 	uint16_t	altBbCredit:1;		/* FC Word 1, bit 27 */
1146 	uint16_t	edtovResolution:1;	/* FC Word 1, bit 26 */
1147 	uint16_t	multicast:1;		/* FC Word 1, bit 25 */
1148 	uint16_t	broadcast:1;		/* FC Word 1, bit 24 */
1149 
1150 	uint16_t	huntgroup:1;		/* FC Word 1, bit 23 */
1151 	uint16_t	simplex:1;		/* FC Word 1, bit 22 */
1152 
1153 	uint16_t	fcsp_support:1;		/* FC Word 1, bit 21 */
1154 	uint16_t	word1Reserved20:1;	/* FC Word 1, bit 20 */
1155 	uint16_t	word1Reserved19:1;	/* FC Word 1, bit 19 */
1156 
1157 	uint16_t	dhd:1;			/* FC Word 1, bit 18 */
1158 	uint16_t	contIncSeqCnt:1;	/* FC Word 1, bit 17 */
1159 	uint16_t	payloadlength:1;	/* FC Word 1, bit 16 */
1160 #endif
1161 #ifdef EMLXS_LITTLE_ENDIAN
1162 	uint16_t	broadcast:1;		/* FC Word 1, bit 24 */
1163 	uint16_t	multicast:1;		/* FC Word 1, bit 25 */
1164 	uint16_t	edtovResolution:1;	/* FC Word 1, bit 26 */
1165 	uint16_t	altBbCredit:1;		/* FC Word 1, bit 27 */
1166 	uint16_t	fPort:1;		/* FC Word 1, bit 28 */
1167 	uint16_t	rspMultipleNPort:1;	/* FC Word 1, bit 29 */
1168 	uint16_t	randomOffset:1;		/* FC Word 1, bit 30 */
1169 	uint16_t	reqMultipleNPort:1;	/* FC Word 1, bit 31 */
1170 
1171 	uint16_t	payloadlength:1;	/* FC Word 1, bit 16 */
1172 	uint16_t	contIncSeqCnt:1;	/* FC Word 1, bit 17 */
1173 	uint16_t	dhd:1;			/* FC Word 1, bit 18 */
1174 
1175 	uint16_t	word1Reserved19:1;	/* FC Word 1, bit 19 */
1176 	uint16_t	word1Reserved20:1;	/* FC Word 1, bit 20 */
1177 	uint16_t	fcsp_support:1;		/* FC Word 1, bit 21 */
1178 
1179 	uint16_t	simplex:1;		/* FC Word 1, bit 22 */
1180 	uint16_t	huntgroup:1;		/* FC Word 1, bit 23 */
1181 #endif
1182 	uint8_t		bbRcvSizeMsb;		/* Upper nibble is reserved */
1183 	uint8_t		bbRcvSizeLsb;		/* FC Word 1, byte 3 */
1184 	union
1185 	{
1186 		struct
1187 		{
1188 			uint8_t	word2Reserved1;	/* FC Word 2 byte 0 */
1189 
1190 			uint8_t	totalConcurrSeq; /* FC Word 2 byte 1 */
1191 			uint8_t	roByCategoryMsb; /* FC Word 2 byte 2 */
1192 
1193 			uint8_t	roByCategoryLsb; /* FC Word 2 byte 3 */
1194 		} nPort;
1195 		uint32_t	r_a_tov;	/* R_A_TOV must be in Big */
1196 						/* Endian format */
1197 	} w2;
1198 
1199 	uint32_t	e_d_tov;		/* E_D_TOV must be in Big */
1200 						/* Endian format */
1201 } emlxs_csp_t;
1202 typedef emlxs_csp_t CSP;
1203 
1204 
1205 typedef struct emlxs_class_parms
1206 {
1207 #ifdef EMLXS_BIG_ENDIAN
1208 	uint8_t	classValid:1;		/* FC Word 0, bit 31 */
1209 	uint8_t	intermix:1;		/* FC Word 0, bit 30 */
1210 	uint8_t	stackedXparent:1;	/* FC Word 0, bit 29 */
1211 	uint8_t	stackedLockDown:1;	/* FC Word 0, bit 28 */
1212 	uint8_t	seqDelivery:1;		/* FC Word 0, bit 27 */
1213 	uint8_t	word0Reserved1:3;	/* FC Word 0, bit 24:26 */
1214 #endif
1215 #ifdef EMLXS_LITTLE_ENDIAN
1216 	uint8_t	word0Reserved1:3;	/* FC Word 0, bit 24:26 */
1217 	uint8_t	seqDelivery:1;		/* FC Word 0, bit 27 */
1218 	uint8_t	stackedLockDown:1;	/* FC Word 0, bit 28 */
1219 	uint8_t	stackedXparent:1;	/* FC Word 0, bit 29 */
1220 	uint8_t	intermix:1;		/* FC Word 0, bit 30 */
1221 	uint8_t	classValid:1;		/* FC Word 0, bit 31 */
1222 
1223 #endif
1224 	uint8_t	word0Reserved2;		/* FC Word 0, bit 16:23 */
1225 #ifdef EMLXS_BIG_ENDIAN
1226 	uint8_t	iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
1227 	uint8_t	iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
1228 	uint8_t	iCtlAck0capable:1;	/* FC Word 0, bit 11 */
1229 	uint8_t	iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
1230 	uint8_t	word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
1231 #endif
1232 #ifdef EMLXS_LITTLE_ENDIAN
1233 	uint8_t	word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
1234 	uint8_t	iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
1235 	uint8_t	iCtlAck0capable:1;	/* FC Word 0, bit 11 */
1236 	uint8_t	iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
1237 	uint8_t	iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
1238 #endif
1239 	uint8_t	word0Reserved4;		/* FC Word 0, bit  0: 7 */
1240 #ifdef EMLXS_BIG_ENDIAN
1241 	uint8_t	rCtlAck0capable:1;	/* FC Word 1, bit 31 */
1242 	uint8_t	rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
1243 	uint8_t	rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
1244 	uint8_t	rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
1245 	uint8_t	word1Reserved1:1;	/* FC Word 1, bit 26 */
1246 	uint8_t	rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
1247 #endif
1248 #ifdef EMLXS_LITTLE_ENDIAN
1249 	uint8_t	rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
1250 	uint8_t	word1Reserved1:1;	/* FC Word 1, bit 26 */
1251 	uint8_t	rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
1252 	uint8_t	rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
1253 	uint8_t	rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
1254 	uint8_t	rCtlAck0capable:1;	/* FC Word 1, bit 31 */
1255 #endif
1256 	uint8_t	word1Reserved2;		/* FC Word 1, bit 16:23 */
1257 	uint8_t	rcvDataSizeMsb;		/* FC Word 1, bit  8:15 */
1258 	uint8_t	rcvDataSizeLsb;		/* FC Word 1, bit  0: 7 */
1259 
1260 	uint8_t	concurrentSeqMsb;	/* FC Word 2, bit 24:31 */
1261 	uint8_t	concurrentSeqLsb;	/* FC Word 2, bit 16:23 */
1262 	uint8_t	EeCreditSeqMsb;		/* FC Word 2, bit  8:15 */
1263 	uint8_t	EeCreditSeqLsb;		/* FC Word 2, bit  0: 7 */
1264 
1265 	uint8_t	openSeqPerXchgMsb;	/* FC Word 3, bit 24:31 */
1266 	uint8_t	openSeqPerXchgLsb;	/* FC Word 3, bit 16:23 */
1267 	uint8_t	word3Reserved1;		/* Fc Word 3, bit  8:15 */
1268 	uint8_t	word3Reserved2;		/* Fc Word 3, bit  0: 7 */
1269 } emlxs_class_parms_t;
1270 typedef emlxs_class_parms_t CLASS_PARMS;
1271 
1272 
1273 typedef struct emlxs_serv_parms
1274 { /* Structure is in Big Endian format */
1275 	CSP		cmn;
1276 	NAME_TYPE	portName;
1277 	NAME_TYPE	nodeName;
1278 	CLASS_PARMS	cls1;
1279 	CLASS_PARMS	cls2;
1280 	CLASS_PARMS	cls3;
1281 	CLASS_PARMS	cls4;
1282 	uint8_t		vendorVersion[16];
1283 } emlxs_serv_parms_t;
1284 typedef emlxs_serv_parms_t SERV_PARM;
1285 
1286 typedef struct
1287 {
1288 	union
1289 	{
1290 		uint32_t	word0;
1291 		struct
1292 		{
1293 #ifdef EMLXS_BIG_ENDIAN
1294 			uint32_t rsvd0:8;	/* Word 0, Byte 3 */
1295 			uint32_t oui:24;	/* Elx Organization */
1296 						/* Unique ID (0000C9) */
1297 #endif
1298 #ifdef EMLXS_LITTLE_ENDIAN
1299 			uint32_t oui:24;	/* Elx Organization */
1300 						/* Unique ID (0000C9) */
1301 			uint32_t rsvd0:8;	/* Word 0, Byte 3 */
1302 #endif
1303 		} w0;
1304 	} un0;
1305 	union
1306 	{
1307 		uint32_t	word1;
1308 		struct
1309 		{
1310 #ifdef EMLXS_BIG_ENDIAN
1311 			uint32_t vport:1;	/* Word 1, Bit 31 */
1312 			uint32_t rsvd1:31;	/* Word 1, Bit 0-30 */
1313 #endif
1314 #ifdef EMLXS_LITTLE_ENDIAN
1315 			uint32_t rsvd1:31;	/* Word 1, Bit 0-30 */
1316 			uint32_t vport:1;	/* Word 1, Bit 31 */
1317 #endif
1318 		} w1;
1319 	} un1;
1320 	uint8_t		rsvd2[8];
1321 } emlxs_vvl_fmt_t;
1322 
1323 #define	VALID_VENDOR_VERSION	cmn.rspMultipleNPort
1324 
1325 
1326 
1327 /*
1328  * Extended Link Service LS_COMMAND codes (Payload BYTE 0)
1329  */
1330 #ifdef EMLXS_BIG_ENDIAN
1331 #define	ELS_CMD_SHIFT	24
1332 #define	ELS_CMD_MASK	0xff000000
1333 #define	ELS_RSP_MASK	0xff000000
1334 #define	ELS_CMD_LS_RJT	0x01000000
1335 #define	ELS_CMD_ACC	0x02000000
1336 #define	ELS_CMD_PLOGI	0x03000000
1337 #define	ELS_CMD_FLOGI	0x04000000
1338 #define	ELS_CMD_LOGO	0x05000000
1339 #define	ELS_CMD_ABTX	0x06000000
1340 #define	ELS_CMD_RCS	0x07000000
1341 #define	ELS_CMD_RES	0x08000000
1342 #define	ELS_CMD_RSS	0x09000000
1343 #define	ELS_CMD_RSI	0x0A000000
1344 #define	ELS_CMD_ESTS	0x0B000000
1345 #define	ELS_CMD_ESTC	0x0C000000
1346 #define	ELS_CMD_ADVC	0x0D000000
1347 #define	ELS_CMD_RTV	0x0E000000
1348 #define	ELS_CMD_RLS	0x0F000000
1349 #define	ELS_CMD_ECHO	0x10000000
1350 #define	ELS_CMD_TEST	0x11000000
1351 #define	ELS_CMD_RRQ	0x12000000
1352 #define	ELS_CMD_REC	0x13000000
1353 #define	ELS_CMD_PRLI	0x20000000
1354 #define	ELS_CMD_PRLO	0x21000000
1355 #define	ELS_CMD_SCN	0x22000000
1356 #define	ELS_CMD_TPLS	0x23000000
1357 #define	ELS_CMD_GPRLO	0x24000000
1358 #define	ELS_CMD_GAID	0x30000000
1359 #define	ELS_CMD_FACT	0x31000000
1360 #define	ELS_CMD_FDACT	0x32000000
1361 #define	ELS_CMD_NACT	0x33000000
1362 #define	ELS_CMD_NDACT	0x34000000
1363 #define	ELS_CMD_QoSR	0x40000000
1364 #define	ELS_CMD_RVCS	0x41000000
1365 #define	ELS_CMD_PDISC	0x50000000
1366 #define	ELS_CMD_FDISC	0x51000000
1367 #define	ELS_CMD_ADISC	0x52000000
1368 #define	ELS_CMD_FARP	0x54000000
1369 #define	ELS_CMD_FARPR	0x55000000
1370 #define	ELS_CMD_FAN	0x60000000
1371 #define	ELS_CMD_RSCN	0x61000000
1372 #define	ELS_CMD_SCR	0x62000000
1373 #define	ELS_CMD_LINIT	0x70000000
1374 #define	ELS_CMD_RNID	0x78000000
1375 #define	ELS_CMD_AUTH	0x90000000
1376 #endif
1377 
1378 #ifdef EMLXS_LITTLE_ENDIAN
1379 #define	ELS_CMD_SHIFT	0
1380 #define	ELS_CMD_MASK	0xff
1381 #define	ELS_RSP_MASK	0xff
1382 #define	ELS_CMD_LS_RJT	0x01
1383 #define	ELS_CMD_ACC	0x02
1384 #define	ELS_CMD_PLOGI	0x03
1385 #define	ELS_CMD_FLOGI	0x04
1386 #define	ELS_CMD_LOGO	0x05
1387 #define	ELS_CMD_ABTX	0x06
1388 #define	ELS_CMD_RCS	0x07
1389 #define	ELS_CMD_RES	0x08
1390 #define	ELS_CMD_RSS	0x09
1391 #define	ELS_CMD_RSI	0x0A
1392 #define	ELS_CMD_ESTS	0x0B
1393 #define	ELS_CMD_ESTC	0x0C
1394 #define	ELS_CMD_ADVC	0x0D
1395 #define	ELS_CMD_RTV	0x0E
1396 #define	ELS_CMD_RLS	0x0F
1397 #define	ELS_CMD_ECHO	0x10
1398 #define	ELS_CMD_TEST	0x11
1399 #define	ELS_CMD_RRQ	0x12
1400 #define	ELS_CMD_REC	0x13
1401 #define	ELS_CMD_PRLI	0x20
1402 #define	ELS_CMD_PRLO	0x21
1403 #define	ELS_CMD_SCN	0x22
1404 #define	ELS_CMD_TPLS	0x23
1405 #define	ELS_CMD_GPRLO	0x24
1406 #define	ELS_CMD_GAID	0x30
1407 #define	ELS_CMD_FACT	0x31
1408 #define	ELS_CMD_FDACT	0x32
1409 #define	ELS_CMD_NACT	0x33
1410 #define	ELS_CMD_NDACT	0x34
1411 #define	ELS_CMD_QoSR	0x40
1412 #define	ELS_CMD_RVCS	0x41
1413 #define	ELS_CMD_PDISC	0x50
1414 #define	ELS_CMD_FDISC	0x51
1415 #define	ELS_CMD_ADISC	0x52
1416 #define	ELS_CMD_FARP	0x54
1417 #define	ELS_CMD_FARPR	0x55
1418 #define	ELS_CMD_FAN	0x60
1419 #define	ELS_CMD_RSCN	0x61
1420 #define	ELS_CMD_SCR	0x62
1421 #define	ELS_CMD_LINIT	0x70
1422 #define	ELS_CMD_RNID	0x78
1423 #define	ELS_CMD_AUTH	0x90
1424 #endif
1425 
1426 
1427 /*
1428  * LS_RJT Payload Definition
1429  */
1430 
1431 typedef struct _LS_RJT
1432 { /* Structure is in Big Endian format */
1433 	union
1434 	{
1435 		uint32_t	lsRjtError;
1436 		struct
1437 		{
1438 			uint8_t	lsRjtRsvd0;	/* FC Word 0, */
1439 						/* bit 24:31 */
1440 
1441 			uint8_t	lsRjtRsnCode;	/* FC Word 0, */
1442 						/* bit 16:23 */
1443 			/* LS_RJT reason codes */
1444 #define	LSRJT_INVALID_CMD	0x01
1445 #define	LSRJT_LOGICAL_ERR	0x03
1446 #define	LSRJT_LOGICAL_BSY	0x05
1447 #define	LSRJT_PROTOCOL_ERR	0x07
1448 #define	LSRJT_UNABLE_TPC	0x09	/* Unable to perform command */
1449 #define	LSRJT_CMD_UNSUPPORTED	0x0B
1450 #define	LSRJT_VENDOR_UNIQUE	0xFF	/* See Byte 3 */
1451 
1452 			uint8_t	lsRjtRsnCodeExp;	/* FC Word 0, */
1453 							/* bit 8:15 */
1454 			/* LS_RJT reason explanation */
1455 #define	LSEXP_NOTHING_MORE	0x00
1456 #define	LSEXP_SPARM_OPTIONS	0x01
1457 #define	LSEXP_SPARM_ICTL	0x03
1458 #define	LSEXP_SPARM_RCTL	0x05
1459 #define	LSEXP_SPARM_RCV_SIZE	0x07
1460 #define	LSEXP_SPARM_CONCUR_SEQ	0x09
1461 #define	LSEXP_SPARM_CREDIT	0x0B
1462 #define	LSEXP_INVALID_PNAME	0x0D
1463 #define	LSEXP_INVALID_NNAME	0x0E
1464 #define	LSEXP_INVALID_CSP	0x0F
1465 #define	LSEXP_INVALID_ASSOC_HDR	0x11
1466 #define	LSEXP_ASSOC_HDR_REQ	0x13
1467 #define	LSEXP_INVALID_O_SID	0x15
1468 #define	LSEXP_INVALID_OX_RX	0x17
1469 #define	LSEXP_CMD_IN_PROGRESS	0x19
1470 #define	LSEXP_INVALID_NPORT_ID	0x1F
1471 #define	LSEXP_INVALID_SEQ_ID	0x21
1472 #define	LSEXP_INVALID_XCHG	0x23
1473 #define	LSEXP_INACTIVE_XCHG	0x25
1474 #define	LSEXP_RQ_REQUIRED	0x27
1475 #define	LSEXP_OUT_OF_RESOURCE	0x29
1476 #define	LSEXP_CANT_GIVE_DATA	0x2A
1477 #define	LSEXP_REQ_UNSUPPORTED	0x2C
1478 			uint8_t	vendorUnique;	/* FC Word 0, bit  0: 7 */
1479 		} b;
1480 	} un;
1481 } LS_RJT;
1482 
1483 
1484 /*
1485  * N_Port Login (FLOGO/PLOGO Request) Payload Definition
1486  */
1487 
1488 typedef struct _LOGO
1489 { /* Structure is in Big Endian format */
1490 	union
1491 	{
1492 		uint32_t	nPortId32;	/* Access nPortId as a word */
1493 		struct
1494 		{
1495 			uint8_t	word1Reserved1;	/* FC Word 1, bit 31:24 */
1496 			uint8_t	nPortIdByte0;	/* N_port  ID bit 16:23 */
1497 			uint8_t	nPortIdByte1;	/* N_port  ID bit  8:15 */
1498 			uint8_t	nPortIdByte2;	/* N_port  ID bit  0: 7 */
1499 		} b;
1500 	} un;
1501 	NAME_TYPE		portName;	/* N_port name field */
1502 } LOGO;
1503 
1504 
1505 /*
1506  * FCP Login (PRLI Request / ACC) Payload Definition
1507  */
1508 
1509 #define	PRLX_PAGE_LEN	0x10
1510 #define	TPRLO_PAGE_LEN	0x14
1511 
1512 typedef struct _PRLI
1513 { /* Structure is in Big Endian format */
1514 	uint8_t		prliType;		/* FC Parm Word 0, bit 24:31 */
1515 
1516 #define	PRLI_FCP_TYPE 0x08
1517 	uint8_t		word0Reserved1;		/* FC Parm Word 0, bit 16:23 */
1518 
1519 #ifdef EMLXS_BIG_ENDIAN
1520 	uint8_t		origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
1521 	uint8_t		respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
1522 	uint8_t		estabImagePair:1;	/* FC Parm Word 0, bit 13 */
1523 
1524 	/* ACC = imagePairEstablished */
1525 	uint8_t		word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
1526 	uint8_t		acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, */
1527 						/* ACC ONLY */
1528 #endif
1529 #ifdef EMLXS_LITTLE_ENDIAN
1530 	uint8_t		acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, */
1531 						/* ACC ONLY */
1532 	uint8_t		word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
1533 	uint8_t		estabImagePair:1;	/* FC Parm Word 0, bit 13 */
1534 	uint8_t		respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
1535 	uint8_t		origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
1536 	/* ACC = imagePairEstablished */
1537 #endif
1538 #define	PRLI_REQ_EXECUTED	0x1		/* acceptRspCode */
1539 #define	PRLI_NO_RESOURCES	0x2
1540 #define	PRLI_INIT_INCOMPLETE	0x3
1541 #define	PRLI_NO_SUCH_PA		0x4
1542 #define	PRLI_PREDEF_CONFIG	0x5
1543 #define	PRLI_PARTIAL_SUCCESS	0x6
1544 #define	PRLI_INVALID_PAGE_CNT	0x7
1545 	uint8_t		word0Reserved3;		/* FC Parm Word 0, bit 0:7 */
1546 
1547 	uint32_t	origProcAssoc;		/* FC Parm Word 1, bit 0:31 */
1548 
1549 	uint32_t	respProcAssoc;		/* FC Parm Word 2, bit 0:31 */
1550 
1551 	uint8_t		word3Reserved1;		/* FC Parm Word 3, bit 24:31 */
1552 	uint8_t		word3Reserved2;		/* FC Parm Word 3, bit 16:23 */
1553 #ifdef EMLXS_BIG_ENDIAN
1554 	uint16_t	Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
1555 	uint16_t	Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
1556 	uint16_t	Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
1557 	uint16_t	Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
1558 	uint16_t	Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
1559 	uint16_t	Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
1560 	uint16_t	TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
1561 	uint16_t	Retry:1;		/* FC Parm Word 3, bit  8 */
1562 	uint16_t	ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
1563 	uint16_t	dataOverLay:1;		/* FC Parm Word 3, bit  6 */
1564 	uint16_t	initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
1565 	uint16_t	targetFunc:1;		/* FC Parm Word 3, bit  4 */
1566 	uint16_t	cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
1567 	uint16_t	dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
1568 	uint16_t	readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
1569 	uint16_t	writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
1570 #endif
1571 #ifdef EMLXS_LITTLE_ENDIAN
1572 	uint16_t	Retry:1;		/* FC Parm Word 3, bit  8 */
1573 	uint16_t	TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
1574 	uint16_t	Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
1575 	uint16_t	Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
1576 	uint16_t	Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
1577 	uint16_t	Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
1578 	uint16_t	Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
1579 	uint16_t	Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
1580 	uint16_t	writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
1581 	uint16_t	readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
1582 	uint16_t	dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
1583 	uint16_t	cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
1584 	uint16_t	targetFunc:1;		/* FC Parm Word 3, bit  4 */
1585 	uint16_t	initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
1586 	uint16_t	dataOverLay:1;		/* FC Parm Word 3, bit  6 */
1587 	uint16_t	ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
1588 #endif
1589 } PRLI;
1590 
1591 /*
1592  * FCP Logout (PRLO Request / ACC) Payload Definition
1593  */
1594 
1595 typedef struct _PRLO
1596 { /* Structure is in Big Endian format */
1597 	uint8_t		prloType;	/* FC Parm Word 0, bit 24:31 */
1598 
1599 #define	PRLO_FCP_TYPE	0x08
1600 	uint8_t		word0Reserved1;	/* FC Parm Word 0, bit 16:23 */
1601 
1602 #ifdef EMLXS_BIG_ENDIAN
1603 	uint8_t		origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
1604 	uint8_t		respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
1605 	uint8_t		word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
1606 	uint8_t		acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, */
1607 						/* ACC ONLY */
1608 #endif
1609 #ifdef EMLXS_LITTLE_ENDIAN
1610 	uint8_t		acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, */
1611 						/* ACC ONLY */
1612 	uint8_t		word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
1613 	uint8_t		respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
1614 	uint8_t		origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
1615 #endif
1616 #define	PRLO_REQ_EXECUTED	0x1		/* acceptRspCode */
1617 #define	PRLO_NO_SUCH_IMAGE	0x4
1618 #define	PRLO_INVALID_PAGE_CNT	0x7
1619 
1620 	uint8_t		word0Reserved3;		/* FC Parm Word 0, bit 0:7 */
1621 	uint32_t	origProcAssoc;		/* FC Parm Word 1, bit 0:31 */
1622 	uint32_t	respProcAssoc;		/* FC Parm Word 2, bit 0:31 */
1623 	uint32_t	word3Reserved1;		/* FC Parm Word 3, bit 0:31 */
1624 } PRLO;
1625 
1626 
1627 typedef struct _ADISC
1628 { /* Structure is in Big Endian format */
1629 	uint32_t	hardAL_PA;
1630 	NAME_TYPE	portName;
1631 	NAME_TYPE	nodeName;
1632 	uint32_t	DID;
1633 } ADISC;
1634 
1635 
1636 typedef struct _FARP
1637 { /* Structure is in Big Endian format */
1638 	uint32_t	Mflags:8;
1639 	uint32_t	Odid:24;
1640 #define	FARP_NO_ACTION	0	/* FARP information enclosed, no action */
1641 #define	FARP_MATCH_PORT	0x1	/* Match on Responder Port Name */
1642 #define	FARP_MATCH_NODE	0x2	/* Match on Responder Node Name */
1643 #define	FARP_MATCH_IP	0x4	/* Match on IP address, not supported */
1644 #define	FARP_MATCH_IPV4	0x5	/* Match on IPV4 address, not supported */
1645 #define	FARP_MATCH_IPV6	0x6	/* Match on IPV6 address, not supported */
1646 	uint32_t	Rflags:8;
1647 	uint32_t	Rdid:24;
1648 #define	FARP_REQUEST_PLOGI	0x1	/* Request for PLOGI */
1649 #define	FARP_REQUEST_FARPR	0x2	/* Request for FARP Response */
1650 	NAME_TYPE	OportName;
1651 	NAME_TYPE	OnodeName;
1652 	NAME_TYPE	RportName;
1653 	NAME_TYPE	RnodeName;
1654 	uint8_t		Oipaddr[16];
1655 	uint8_t		Ripaddr[16];
1656 } FARP;
1657 
1658 typedef struct _FAN
1659 { /* Structure is in Big Endian format */
1660 	uint32_t	Fdid;
1661 	NAME_TYPE	FportName;
1662 	NAME_TYPE	FnodeName;
1663 } FAN;
1664 
1665 typedef struct _SCR
1666 { /* Structure is in Big Endian format */
1667 	uint8_t		resvd1;
1668 	uint8_t		resvd2;
1669 	uint8_t		resvd3;
1670 	uint8_t		Function;
1671 #define	SCR_FUNC_FABRIC	0x01
1672 #define	SCR_FUNC_NPORT	0x02
1673 #define	SCR_FUNC_FULL	0x03
1674 #define	SCR_CLEAR	0xff
1675 } SCR;
1676 
1677 typedef struct _RNID_TOP_DISC
1678 {
1679 	NAME_TYPE	portName;
1680 	uint8_t		resvd[8];
1681 	uint32_t	unitType;
1682 #define	RNID_HBA	0x7
1683 #define	RNID_HOST	0xa
1684 #define	RNID_DRIVER	0xd
1685 	uint32_t	physPort;
1686 	uint32_t	attachedNodes;
1687 	uint16_t	ipVersion;
1688 #define	RNID_IPV4	0x1
1689 #define	RNID_IPV6	0x2
1690 	uint16_t	UDPport;
1691 	uint8_t		ipAddr[16];
1692 	uint16_t	resvd1;
1693 	uint16_t	flags;
1694 #define	RNID_TD_SUPPORT	0x1
1695 #define	RNID_LP_VALID	0x2
1696 } RNID_TOP_DISC;
1697 
1698 typedef struct _RNID
1699 { /* Structure is in Big Endian format */
1700 	uint8_t		Format;
1701 #define	RNID_TOPOLOGY_DISC  0xdf
1702 	uint8_t		CommonLen;
1703 	uint8_t		resvd1;
1704 	uint8_t		SpecificLen;
1705 	NAME_TYPE	portName;
1706 	NAME_TYPE	nodeName;
1707 	union
1708 	{
1709 		RNID_TOP_DISC topologyDisc;	/* topology disc (0xdf) */
1710 	} un;
1711 } RNID;
1712 
1713 typedef struct _RRQ
1714 { /* Structure is in Big Endian format */
1715 	uint32_t	SID;
1716 	uint16_t	Oxid;
1717 	uint16_t	Rxid;
1718 	uint8_t		resv[32];	/* optional association hdr */
1719 } RRQ;
1720 
1721 
1722 /* This is used for RSCN command */
1723 typedef struct _D_ID
1724 { /* Structure is in Big Endian format */
1725 	union
1726 	{
1727 		uint32_t	word;
1728 		struct
1729 		{
1730 #ifdef EMLXS_BIG_ENDIAN
1731 			uint8_t	resv;
1732 			uint8_t	domain;
1733 			uint8_t	area;
1734 			uint8_t	id;
1735 #endif
1736 #ifdef EMLXS_LITTLE_ENDIAN
1737 			uint8_t	id;
1738 			uint8_t	area;
1739 			uint8_t	domain;
1740 			uint8_t	resv;
1741 #endif
1742 		} b;
1743 	} un;
1744 } D_ID;
1745 
1746 /*
1747  * Structure to define	all ELS Payload types
1748  */
1749 
1750 typedef struct _ELS_PKT
1751 { /* Structure is in Big Endian format */
1752 	uint8_t		elsCode;		/* FC Word 0, bit 24:31 */
1753 	uint8_t		elsByte1;
1754 	uint8_t		elsByte2;
1755 	uint8_t		elsByte3;
1756 	union
1757 	{
1758 		LS_RJT		lsRjt;		/* Payload for LS_RJT */
1759 		SERV_PARM	logi;		/* Payload for PLOGI, FLOGI */
1760 						/* PDISC, ACC */
1761 		LOGO		logo;		/* Payload for PLOGO, FLOGO */
1762 						/* ACC */
1763 		PRLI		prli;		/* Payload for PRLI/ACC */
1764 		PRLO		prlo;		/* Payload for PRLO/ACC */
1765 		ADISC		adisc;		/* Payload for ADISC/ACC */
1766 		FARP		farp;		/* Payload for FARP/ACC */
1767 		FAN		fan;		/* Payload for FAN */
1768 		SCR		scr;		/* Payload for SCR/ACC */
1769 		RRQ		rrq;		/* Payload for RRQ */
1770 		RNID		rnid;		/* Payload for RNID */
1771 		uint8_t		pad[128 - 4];	/* Pad out to payload of */
1772 						/* 128 bytes */
1773 	} un;
1774 } ELS_PKT;
1775 
1776 
1777 typedef struct
1778 {
1779 	uint32_t	bdeAddress;
1780 #ifdef EMLXS_BIG_ENDIAN
1781 	uint32_t	bdeReserved:4;
1782 	uint32_t	bdeAddrHigh:4;
1783 	uint32_t	bdeSize:24;
1784 #endif
1785 #ifdef EMLXS_LITTLE_ENDIAN
1786 	uint32_t	bdeSize:24;
1787 	uint32_t	bdeAddrHigh:4;
1788 	uint32_t	bdeReserved:4;
1789 #endif
1790 } ULP_BDE;
1791 
1792 typedef struct ULP_BDE_64
1793 { /* SLI-2 */
1794 	union ULP_BDE_TUS
1795 	{
1796 		uint32_t	w;
1797 		struct
1798 		{
1799 #ifdef EMLXS_BIG_ENDIAN
1800 			uint32_t	bdeFlags:8;	/* BDE Flags 0 IS A */
1801 							/* SUPPORTED VALUE !! */
1802 			uint32_t	bdeSize:24;	/* buff size in bytes */
1803 #endif
1804 #ifdef EMLXS_LITTLE_ENDIAN
1805 			uint32_t	bdeSize:24;	/* buff size in bytes */
1806 			uint32_t	bdeFlags:8;	/* BDE Flags 0 IS A */
1807 							/* SUPPORTED VALUE !! */
1808 #endif
1809 #define	BUFF_USE_RSVD		0x01	/* bdeFlags */
1810 #define	BUFF_USE_INTRPT		0x02	/* Not Implemented with LP6000 */
1811 #define	BUFF_USE_CMND		0x04	/* Optional, 1=cmd/rsp 0=data buffer */
1812 #define	BUFF_USE_RCV		0x08	/* ""  "", 1=rcv buffer, */
1813 					/* 0=xmit buffer */
1814 #define	BUFF_TYPE_32BIT		0x10	/* ""  "", 1=32 bit addr */
1815 					/* 0=64 bit addr */
1816 #define	BUFF_TYPE_SPECIAL	0x20	/* Not Implemented with LP6000  */
1817 #define	BUFF_TYPE_BDL		0x40	/* Optional,  may be set in BDL */
1818 #define	BUFF_TYPE_INVALID	0x80	/* ""  "" */
1819 		} f;
1820 	} tus;
1821 	uint32_t	addrLow;
1822 	uint32_t	addrHigh;
1823 } ULP_BDE64;
1824 
1825 #define	BDE64_SIZE_WORD	0
1826 #define	BPL64_SIZE_WORD	0x40
1827 
1828 /*  ULP  */
1829 typedef struct ULP_BPL_64
1830 {
1831 	ULP_BDE64	fccmd_payload;
1832 	ULP_BDE64	fcrsp_payload;
1833 	ULP_BDE64	fcdat_payload;
1834 	ULP_BDE64	pat0;
1835 } ULP_BPL64;
1836 
1837 typedef struct ULP_BDL
1838 { /* SLI-2 */
1839 #ifdef EMLXS_BIG_ENDIAN
1840 	uint32_t	bdeFlags:8;	/* BDL Flags */
1841 	uint32_t	bdeSize:24;	/* Size of BDL array in host */
1842 					/* memory (bytes) */
1843 #endif
1844 #ifdef EMLXS_LITTLE_ENDIAN
1845 	uint32_t	bdeSize:24;	/* Size of BDL array in host */
1846 					/* memory (bytes) */
1847 	uint32_t	bdeFlags:8;	/* BDL Flags */
1848 #endif
1849 	uint32_t	addrLow;	/* Address 0:31 */
1850 	uint32_t	addrHigh;	/* Address 32:63 */
1851 	uint32_t	ulpIoTag32;	/* Can be used for 32 bit I/O Tag */
1852 } ULP_BDL;
1853 
1854 typedef struct ULP_SGE_64
1855 { /* SLI-4 */
1856 	uint32_t	addrHigh;	/* Address 32:63 */
1857 	uint32_t	addrLow;	/* Address 0:31 */
1858 #ifdef EMLXS_BIG_ENDIAN
1859 	uint32_t	last:1;		/* Last entry in SGL */
1860 	uint32_t	type:4;
1861 	uint32_t	offset:27;
1862 #endif
1863 #ifdef EMLXS_LITTLE_ENDIAN
1864 	uint32_t	offset:27;
1865 	uint32_t	type:4;
1866 	uint32_t	last:1;		/* Last entry in SGL */
1867 #endif
1868 #define	EMLXS_SGE_TYPE_DATA	0x0
1869 #define	EMLXS_SGE_TYPE_DIF	0x4
1870 #define	EMLXS_SGE_TYPE_LSP	0x5
1871 #define	EMLXS_SGE_TYPE_ENC_DIF	0x6
1872 #define	EMLXS_SGE_TYPE_ENC_SEED	0x7
1873 #define	EMLXS_SGE_TYPE_SEED	0x8
1874 #define	EMLXS_SGE_TYPE_ENC	0x9
1875 #define	EMLXS_SGE_TYPE_SKIP	0xC
1876 
1877 	uint32_t	length;
1878 #define	EMLXS_MAX_SGE_SIZE	0x10000	/* 64K max length */
1879 } ULP_SGE64;
1880 
1881 #define	EMLXS_XFER_RDY_SIZE	12  /* Payload size of a FCP Transfer Ready */
1882 
1883 typedef	struct _BE_PHYS_ADDR
1884 {
1885 	uint32_t	addrLow;
1886 	uint32_t	addrHigh;
1887 } BE_PHYS_ADDR;
1888 
1889 
1890 typedef struct
1891 {
1892 	void		*fc_mptr;
1893 	struct emlxs_memseg *segment;	/* Parent segment */
1894 
1895 	void		*virt;		/* virtual address ptr */
1896 	uint64_t	phys;		/* mapped address */
1897 	uint32_t	size;
1898 
1899 	void		*data_handle;
1900 	void		*dma_handle;
1901 	uint32_t	tag;
1902 	uint32_t	flag;
1903 #define	MAP_POOL_ALLOCATED	0x00000001
1904 #define	MAP_BUF_ALLOCATED	0x00000002
1905 #define	MAP_TABLE_ALLOCATED	0x00000004
1906 
1907 #ifdef SFCT_SUPPORT
1908 	void		*fct_private;
1909 #endif /* SFCT_SUPPORT */
1910 } MATCHMAP;
1911 
1912 
1913 /*
1914  * This file defines the Header File for the FDMI HBA Management Service
1915  */
1916 
1917 /*
1918  * FDMI HBA MAnagement Operations Command Codes
1919  */
1920 #define	SLI_MGMT_GRHL	0x100	/* Get registered HBA list */
1921 #define	SLI_MGMT_GHAT	0x101	/* Get HBA attributes */
1922 #define	SLI_MGMT_GRPL	0x102	/* Get registered Port list */
1923 #define	SLI_MGMT_GPAT	0x110	/* Get Port attributes */
1924 #define	SLI_MGMT_RHBA	0x200	/* Register HBA */
1925 #define	SLI_MGMT_RHAT	0x201	/* Register HBA atttributes */
1926 #define	SLI_MGMT_RPRT	0x210	/* Register Port */
1927 #define	SLI_MGMT_RPA	0x211	/* Register Port attributes */
1928 #define	SLI_MGMT_DHBA	0x300	/* De-register HBA */
1929 #define	SLI_MGMT_DPRT	0x310	/* De-register Port */
1930 
1931 /*
1932  * Management Service Subtypes
1933  */
1934 #define	SLI_CT_FDMI_SUBTYPES	0x10
1935 
1936 
1937 /*
1938  * HBA Management Service Reject Code
1939  */
1940 #define	REJECT_CODE		0x9	/* Unable to perform command request */
1941 
1942 /*
1943  * HBA Management Service Reject Reason Code
1944  * Please refer to the Reason Codes above
1945  */
1946 
1947 /*
1948  * HBA Attribute Types
1949  */
1950 #define	NODE_NAME		0x1
1951 #define	MANUFACTURER		0x2
1952 #define	SERIAL_NUMBER		0x3
1953 #define	MODEL			0x4
1954 #define	MODEL_DESCRIPTION	0x5
1955 #define	HARDWARE_VERSION	0x6
1956 #define	DRIVER_VERSION		0x7
1957 #define	OPTION_ROM_VERSION	0x8
1958 #define	FIRMWARE_VERSION	0x9
1959 #define	VENDOR_SPECIFIC		0xa
1960 #define	DRV_NAME		0xb
1961 #define	OS_NAME_VERSION		0xc
1962 #define	MAX_CT_PAYLOAD_LEN	0xd
1963 
1964 /*
1965  * Port Attrubute Types
1966  */
1967 #define	SUPPORTED_FC4_TYPES	0x1
1968 #define	SUPPORTED_SPEED		0x2
1969 #define	PORT_SPEED		0x3
1970 #define	MAX_FRAME_SIZE		0x4
1971 #define	OS_DEVICE_NAME		0x5
1972 
1973 union AttributesDef
1974 {
1975 	/* Structure is in Big Endian format */
1976 	struct
1977 	{
1978 		uint32_t	AttrType:16;
1979 		uint32_t	AttrLen:16;
1980 	} bits;
1981 	uint32_t	word;
1982 };
1983 
1984 /*
1985  * HBA Attribute Entry (8 - 260 bytes)
1986  */
1987 typedef struct
1988 {
1989 	union AttributesDef	ad;
1990 	union
1991 	{
1992 		uint32_t	VendorSpecific;
1993 		uint32_t	SupportSpeed;
1994 		uint32_t	PortSpeed;
1995 		uint32_t	MaxFrameSize;
1996 		uint32_t	MaxCTPayloadLen;
1997 		uint8_t		SupportFC4Types[32];
1998 		uint8_t		OsDeviceName[256];
1999 		uint8_t		Manufacturer[64];
2000 		uint8_t		SerialNumber[64];
2001 		uint8_t		Model[256];
2002 		uint8_t		ModelDescription[256];
2003 		uint8_t		HardwareVersion[256];
2004 		uint8_t		DriverVersion[256];
2005 		uint8_t		OptionROMVersion[256];
2006 		uint8_t		FirmwareVersion[256];
2007 		uint8_t		DriverName[256];
2008 		NAME_TYPE	NodeName;
2009 	} un;
2010 } ATTRIBUTE_ENTRY, *PATTRIBUTE_ENTRY;
2011 
2012 
2013 /*
2014  * HBA Attribute Block
2015  */
2016 typedef struct
2017 {
2018 	uint32_t	EntryCnt;	/* Number of HBA attribute entries */
2019 	ATTRIBUTE_ENTRY	Entry;		/* Variable-length array */
2020 } ATTRIBUTE_BLOCK, *PATTRIBUTE_BLOCK;
2021 
2022 
2023 /*
2024  * Port Entry
2025  */
2026 typedef struct
2027 {
2028 	NAME_TYPE	PortName;
2029 } PORT_ENTRY, *PPORT_ENTRY;
2030 
2031 /*
2032  * HBA Identifier
2033  */
2034 typedef struct
2035 {
2036 	NAME_TYPE	PortName;
2037 } HBA_IDENTIFIER, *PHBA_IDENTIFIER;
2038 
2039 /*
2040  * Registered Port List Format
2041  */
2042 typedef struct
2043 {
2044 	uint32_t	EntryCnt;
2045 	PORT_ENTRY	pe;	/* Variable-length array */
2046 } REG_PORT_LIST, *PREG_PORT_LIST;
2047 
2048 /*
2049  * Register HBA(RHBA)
2050  */
2051 typedef struct
2052 {
2053 	HBA_IDENTIFIER	hi;
2054 	REG_PORT_LIST	rpl;	/* variable-length array */
2055 } REG_HBA, *PREG_HBA;
2056 
2057 /*
2058  * Register HBA Attributes (RHAT)
2059  */
2060 typedef struct
2061 {
2062 	NAME_TYPE	HBA_PortName;
2063 	ATTRIBUTE_BLOCK	ab;
2064 } REG_HBA_ATTRIBUTE, *PREG_HBA_ATTRIBUTE;
2065 
2066 /*
2067  * Register Port Attributes (RPA)
2068  */
2069 typedef struct
2070 {
2071 	NAME_TYPE	HBA_PortName;
2072 	NAME_TYPE	PortName;
2073 	ATTRIBUTE_BLOCK	ab;
2074 } REG_PORT_ATTRIBUTE, *PREG_PORT_ATTRIBUTE;
2075 
2076 /*
2077  * Get Registered HBA List (GRHL) Accept Payload Format
2078  */
2079 typedef struct
2080 {
2081 	uint32_t	HBA__Entry_Cnt;	/* Number of Registered HBA Ids */
2082 	NAME_TYPE	HBA_PortName;	/* Variable-length array */
2083 } GRHL_ACC_PAYLOAD, *PGRHL_ACC_PAYLOAD;
2084 
2085 /*
2086  * Get Registered Port List (GRPL) Accept Payload Format
2087  */
2088 typedef struct
2089 {
2090 	uint32_t	RPL_Entry_Cnt;		/* No of Reg Port Entries */
2091 	PORT_ENTRY	eg_Port_Entry[1];	/* Variable-length array */
2092 } GRPL_ACC_PAYLOAD, *PGRPL_ACC_PAYLOAD;
2093 
2094 /*
2095  * Get Port Attributes (GPAT) Accept Payload Format
2096  */
2097 
2098 typedef struct
2099 {
2100 	ATTRIBUTE_BLOCK	pab;
2101 } GPAT_ACC_PAYLOAD, *PGPAT_ACC_PAYLOAD;
2102 
2103 /*
2104  * Use for Firmware DownLoad
2105  */
2106 
2107 /* download.h */
2108 
2109 #define	REDUCED_SRAM_CFG	0x7FFFC	/* 9802DC */
2110 #define	FULL_SRAM_CFG		0x13FFFC	/* 9802   */
2111 
2112 #define	SLI_FW_TYPE_SHIFT(x) ((x << 20))
2113 #define	SLI_FW_ADAPTER_TYPE_MASK   0x00f00000
2114 #define	SLI_FW_TYPE_6000  SLI_FW_TYPE_SHIFT(0)
2115 #define	SLI_FW_TYPE_7000  SLI_FW_TYPE_SHIFT(1)
2116 #define	SLI_FW_TYPE_8000  SLI_FW_TYPE_SHIFT(2)
2117 #define	SLI_FW_TYPE_850   SLI_FW_TYPE_SHIFT(3)
2118 #define	SLI_FW_TYPE_9000  SLI_FW_TYPE_SHIFT(4)
2119 #define	SLI_FW_TYPE_950   SLI_FW_TYPE_SHIFT(5)
2120 #define	SLI_FW_TYPE_9802  SLI_FW_TYPE_SHIFT(6)	/* [022702] */
2121 #define	SLI_FW_TYPE_982   SLI_FW_TYPE_SHIFT(7)
2122 #define	SLI_FW_TYPE_10000 SLI_FW_TYPE_SHIFT(8)
2123 #define	SLI_FW_TYPE_1050  SLI_FW_TYPE_SHIFT(9)
2124 #define	SLI_FW_TYPE_X1000 SLI_FW_TYPE_SHIFT(0xa)
2125 #define	SLI_FW_TYPE_101   SLI_FW_TYPE_SHIFT(0xb)	/* LP101 */
2126 
2127 
2128 enum emlxs_prog_type
2129 {
2130 	TEST_PROGRAM,	/* 0 */
2131 	UTIL_PROGRAM,	/* 1 */
2132 	FUNC_FIRMWARE,	/* 2 */
2133 	BOOT_BIOS,	/* 3 */
2134 	CONFIG_DATA,	/* 4 */
2135 	SEQUENCER_CODE,	/* 5 */
2136 	SLI1_OVERLAY,	/* 6 */
2137 	SLI2_OVERLAY,	/* 7 */
2138 	GASKET,		/* 8 */
2139 	HARDWARE_IMAGE,	/* 9 */
2140 	SBUS_FCODE,	/* A */
2141 	SLI3_OVERLAY,	/* B */
2142 	RESERVED_C,
2143 	RESERVED_D,
2144 	SLI4_OVERLAY,	/* E */
2145 	KERNEL_CODE,	/* F */
2146 	MAX_PROG_TYPES
2147 } emlxs_prog_type_t;
2148 
2149 
2150 typedef struct emlxs_fw_file
2151 {
2152 	uint32_t	version;
2153 	uint32_t	revcomp;
2154 	char		label[16];
2155 	uint32_t	offset;
2156 } emlxs_fw_file_t;
2157 
2158 typedef struct emlxs_fw_image
2159 {
2160 	emlxs_fw_file_t awc;
2161 	emlxs_fw_file_t bwc;
2162 	emlxs_fw_file_t dwc;
2163 	emlxs_fw_file_t prog[MAX_PROG_TYPES];
2164 } emlxs_fw_image_t;
2165 
2166 
2167 
2168 #define	NOP_IMAGE_TYPE		0xe1a00000
2169 
2170 #define	FLASH_BASE_ADR		0x01400000
2171 #define	DL_FROM_SLIM_OFFSET	MBOX_EXTENSION_OFFSET
2172 
2173 #ifdef MBOX_EXT_SUPPORT
2174 #define	DL_SLIM_SEG_BYTE_COUNT	MBOX_EXTENSION_SIZE
2175 #else
2176 #define	DL_SLIM_SEG_BYTE_COUNT	128
2177 #endif /* MBOX_EXT_SUPPORT */
2178 
2179 #define	SLI_CKSUM_LENGTH	4
2180 #define	SLI_CKSUM_SEED		0x55555555
2181 #define	SLI_CKSUM_ERR		0x1982abcd
2182 
2183 #define	AIF_NOOP		0xe1a00000
2184 #define	AIF_BLAL		0xeb000000
2185 #define	OS_EXIT			0xef000011
2186 #define	OS_GETENV		0xef000010
2187 #define	AIF_IMAGEBASE		0x00008000
2188 #define	AIF_BLZINIT		0xeb00000c
2189 #define	DEBUG_TASK		0xef041d41
2190 #define	AIF_DBG_SRC		2
2191 #define	AIF_DBG_LL		1
2192 #define	AIF_DATABASAT		0x100
2193 
2194 #define	JEDEC_ID_ADDRESS	0x0080001c
2195 #define	MAX_RBUS_SRAM_SIZE_ADR	0x788
2196 #define	MAX_IBUS_SRAM_SIZE_ADR	0x78c
2197 #define	FULL_RBUS_SRAM_CFG	0x7fffc
2198 #define	FULL_IBUS_SRAM_CFG	0x187fffc
2199 #define	REDUCED_RBUS_SRAM_CFG	0x5fffc
2200 #define	REDUCED_IBUS_SRAM_CFG	0x183fffc
2201 
2202 #define	FULL_SRAM_CFG_PROG_ID		1
2203 #define	REDUCED_SRAM_CFG_PROG_ID	2
2204 #define	OTHER_SRAM_CFG_PROG_ID		3
2205 
2206 #define	NO_FLASH_MEM_AVAIL	0xf1
2207 
2208 #define	PROG_TYPE_MASK		0xff000000
2209 #define	PROG_TYPE_SHIFT		24
2210 
2211 #define	FLASH_LOAD_LIST_ADR	0x79c
2212 #define	RAM_LOAD_ENTRY_SIZE	9
2213 #define	FLASH_LOAD_ENTRY_SIZE	6
2214 #define	RAM_LOAD_ENTRY_TYPE	0
2215 #define	FLASH_LOAD_ENTRY_TYPE	1
2216 
2217 #define	CFG_DATA_NO_REGION	-3
2218 
2219 #define	SLI_IMAGE_START		0x20080
2220 #define	SLI_VERSION_LOC		0x270
2221 
2222 
2223 #define	SLI_HW_REVISION_CHECK(x, y)	((x & 0xf0) == y)
2224 #define	SLI_FCODE_REVISION_CHECK(x, y)	(x == y)
2225 
2226 
2227 /* ************ OBJ firmware ************** */
2228 #define	OBJ_MAX_XFER_SIZE	32768
2229 
2230 
2231 /* ************ BladeEngine ************** */
2232 #define	BE_SIGNATURE		"ServerEngines"
2233 #define	BE_DIR_SIGNATURE	"*** SE FLAS"
2234 #define	BE_BUILD_SIZE		24
2235 #define	BE_VERSION_SIZE		32
2236 #define	BE_COOKIE_SIZE		32
2237 #define	BE_CONTROLLER_SIZE	8
2238 #define	BE_FLASH_ENTRIES	32
2239 #define	BE_MAX_XFER_SIZE	32768 /* 4K aligned */
2240 
2241 /* ************** BE3 **************** */
2242 #define	BE3_SIGNATURE_SIZE	52
2243 #define	BE3_MAX_IMAGE_HEADERS	32
2244 
2245 typedef struct emlxs_be3_image_header
2246 {
2247 	uint32_t id;
2248 #define	UFI_BE3_FLASH_ID	0x01
2249 
2250 	uint32_t offset;
2251 	uint32_t length;
2252 	uint32_t checksum;
2253 	uint8_t version[BE_VERSION_SIZE];
2254 
2255 } emlxs_be3_image_header_t;
2256 
2257 typedef struct emlxs_be3_ufi_header
2258 {
2259 	char signature[BE3_SIGNATURE_SIZE];
2260 	uint32_t ufi_version;
2261 	uint32_t file_length;
2262 	uint32_t checksum;
2263 	uint32_t antidote;
2264 	uint32_t image_cnt;
2265 	char build[BE_BUILD_SIZE];
2266 	uint8_t resv1[32];
2267 
2268 } emlxs_be3_ufi_header_t;
2269 
2270 typedef struct emlxs_be3_ufi_controller
2271 {
2272 	uint32_t vendor_id;
2273 	uint32_t device_id;
2274 	uint32_t sub_vendor_id;
2275 	uint32_t sub_device_id;
2276 
2277 } emlxs_be3_ufi_controller_t;
2278 
2279 typedef struct emlxs_be3_flash_header
2280 {
2281 	uint32_t format_rev;
2282 	uint32_t checksum;
2283 	uint32_t antidote;
2284 	uint32_t entry_count;
2285 	emlxs_be3_ufi_controller_t controller[BE_CONTROLLER_SIZE];
2286 	uint32_t resv0;
2287 	uint32_t resv1;
2288 	uint32_t resv2;
2289 	uint32_t resv3;
2290 } emlxs_be3_flash_header_t;
2291 
2292 typedef struct emlxs_be3_flash_entry
2293 {
2294 	uint32_t type;
2295 	uint32_t offset;
2296 	uint32_t block_size;
2297 	uint32_t image_size;
2298 	uint32_t checksum;
2299 	uint32_t entry_point;
2300 	uint32_t resv0;
2301 	uint32_t resv1;
2302 	char version[BE_VERSION_SIZE];
2303 
2304 } emlxs_be3_flash_entry_t;
2305 
2306 typedef struct emlxs_be3_flash_dir
2307 {
2308 	char cookie[BE_COOKIE_SIZE];
2309 	emlxs_be3_flash_header_t header;
2310 	emlxs_be3_flash_entry_t entry[BE_FLASH_ENTRIES];
2311 
2312 } emlxs_be3_flash_dir_t;
2313 
2314 typedef struct emlxs_be3_ncsi_header {
2315 	uint32_t magic;
2316 	uint8_t hdr_len;
2317 	uint8_t type;
2318 	uint16_t hdr_ver;
2319 	uint16_t rsvd0;
2320 	uint16_t load_offset;
2321 	uint32_t len;
2322 	uint32_t flash_offset;
2323 	uint8_t ver[16];
2324 	uint8_t name[24];
2325 	uint32_t img_cksum;
2326 	uint32_t rsvd1;
2327 	uint32_t hdr_cksum;
2328 } emlxs_be3_ncsi_header_t;
2329 
2330 
2331 /* ************** BE2 **************** */
2332 #define	BE2_SIGNATURE_SIZE	32
2333 
2334 
2335 typedef struct emlxs_be2_ufi_controller
2336 {
2337 	uint32_t vendor_id;
2338 	uint32_t device_id;
2339 	uint32_t sub_vendor_id;
2340 	uint32_t sub_device_id;
2341 
2342 } emlxs_be2_ufi_controller_t;
2343 
2344 typedef struct emlxs_be2_ufi_header
2345 {
2346 	char signature[BE2_SIGNATURE_SIZE];
2347 	uint32_t checksum;
2348 	uint32_t antidote;
2349 	emlxs_be2_ufi_controller_t  controller;
2350 	uint32_t file_length;
2351 	uint32_t chunk_num;
2352 	uint32_t chunk_cnt;
2353 	uint32_t image_cnt;
2354 	char build[BE_BUILD_SIZE];
2355 
2356 } emlxs_be2_ufi_header_t;
2357 
2358 typedef struct emlxs_be2_flash_header /* 96 bytes */
2359 {
2360 	uint32_t format_rev;
2361 	uint32_t checksum;
2362 	uint32_t antidote;
2363 	uint32_t build_num;
2364 	emlxs_be2_ufi_controller_t controller[BE_CONTROLLER_SIZE];
2365 	uint32_t active_entry_mask;
2366 	uint32_t valid_entry_mask;
2367 	uint32_t orig_content_mask;
2368 	uint32_t resv0;
2369 	uint32_t resv1;
2370 	uint32_t resv2;
2371 	uint32_t resv3;
2372 	uint32_t resv4;
2373 
2374 } emlxs_be2_flash_header_t;
2375 
2376 typedef struct emlxs_be2_flash_entry
2377 {
2378 	uint32_t type;
2379 	uint32_t offset;
2380 	uint32_t pad_size;
2381 	uint32_t image_size;
2382 	uint32_t checksum;
2383 	uint32_t entry_point;
2384 	uint32_t resv0;
2385 	uint32_t resv1;
2386 	char version[BE_VERSION_SIZE];
2387 
2388 } emlxs_be2_flash_entry_t;
2389 
2390 typedef struct emlxs_be2_flash_dir
2391 {
2392 	char cookie[BE_COOKIE_SIZE];
2393 	emlxs_be2_flash_header_t header;
2394 	emlxs_be2_flash_entry_t entry[BE_FLASH_ENTRIES];
2395 
2396 } emlxs_be2_flash_dir_t;
2397 
2398 
2399 /* FLASH ENTRY TYPES */
2400 #define	BE_FLASHTYPE_NCSI_FIRMWARE		0x10 /* BE3 */
2401 #define	BE_FLASHTYPE_PXE_BIOS			0x20
2402 #define	BE_FLASHTYPE_FCOE_BIOS			0x21
2403 #define	BE_FLASHTYPE_ISCSI_BIOS			0x22
2404 #define	BE_FLASHTYPE_FLASH_ISM			0x30 /* BE3 */
2405 #define	BE_FLASHTYPE_ISCSI_FIRMWARE		0xA0
2406 #define	BE_FLASHTYPE_ISCSI_FIRMWARE_COMP	0xA1
2407 #define	BE_FLASHTYPE_FCOE_FIRMWARE		0xA2
2408 #define	BE_FLASHTYPE_FCOE_FIRMWARE_COMP		0xA3
2409 #define	BE_FLASHTYPE_ISCSI_BACKUP		0xB0
2410 #define	BE_FLASHTYPE_ISCSI_BACKUP_COMP		0xB1
2411 #define	BE_FLASHTYPE_FCOE_BACKUP		0xB2
2412 #define	BE_FLASHTYPE_FCOE_BACKUP_COMP		0xB3
2413 #define	BE_FLASHTYPE_PHY_FIRMWARE		0xC0 /* 10Base-T */
2414 #define	BE_FLASHTYPE_REDBOOT			0xE0
2415 
2416 /* Flash types in download order */
2417 typedef enum emlxs_be_flashtypes
2418 {
2419 	PHY_FIRMWARE_FLASHTYPE,
2420 	NCSI_FIRMWARE_FLASHTYPE,
2421 	ISCSI_FIRMWARE_FLASHTYPE,
2422 	ISCSI_BACKUP_FLASHTYPE,
2423 	FCOE_FIRMWARE_FLASHTYPE,
2424 	FCOE_BACKUP_FLASHTYPE,
2425 	ISCSI_BIOS_FLASHTYPE,
2426 	FCOE_BIOS_FLASHTYPE,
2427 	PXE_BIOS_FLASHTYPE,
2428 	REDBOOT_FLASHTYPE,
2429 	BE_MAX_FLASHTYPES
2430 
2431 } emlxs_be_flashtypes_t;
2432 
2433 /* Driver level constructs */
2434 typedef struct emlxs_be_fw_file
2435 {
2436 	uint32_t 	be_version;
2437 	uint32_t	ufi_plus;
2438 
2439 	uint32_t	type;
2440 	uint32_t	image_offset;
2441 	uint32_t	image_size;
2442 	uint32_t	block_size;
2443 	uint32_t	block_crc;
2444 	uint32_t	load_address; /* BE3 */
2445 	char		label[BE_VERSION_SIZE];
2446 } emlxs_be_fw_file_t;
2447 
2448 typedef struct emlxs_be_fw_image
2449 {
2450 	uint32_t 	be_version;
2451 	uint32_t	ufi_plus;
2452 
2453 	uint32_t fcoe_version;
2454 	char fcoe_label[BE_VERSION_SIZE];
2455 
2456 	uint32_t iscsi_version;
2457 	char iscsi_label[BE_VERSION_SIZE];
2458 
2459 	emlxs_be_fw_file_t file[BE_MAX_FLASHTYPES];
2460 } emlxs_be_fw_image_t;
2461 
2462 
2463 typedef struct emlxs_obj_header
2464 {
2465 	uint32_t 	FileSize;
2466 
2467 #ifdef EMLXS_BIG_ENDIAN
2468 	uint16_t 	MagicNumHi;
2469 	uint16_t 	MagicNumLo;
2470 
2471 	uint32_t 	FileType:8;
2472 	uint32_t 	Id:8;
2473 	uint32_t 	rsvd0:16;
2474 #endif
2475 
2476 #ifdef EMLXS_LITTLE_ENDIAN
2477 	uint16_t 	MagicNumLo;
2478 	uint16_t 	MagicNumHi;
2479 
2480 	uint32_t 	rsvd0:16;
2481 	uint32_t 	Id:8;
2482 	uint32_t 	FileType:8;
2483 #endif
2484 
2485 #define	OBJ_MAGIC_NUM_HI		0xFEAA
2486 #define	OBJ_MAGIC_NUM_LO		0x0001
2487 
2488 #define	OBJ_GRP_FILE_TYPE		0xF7
2489 
2490 #define	OBJ_LANCER_ID			0xA2
2491 
2492 	char		RevName[128];
2493 	char		Date[12];
2494 	char		Revision[32];
2495 } emlxs_obj_header_t;
2496 
2497 
2498 #ifdef	__cplusplus
2499 }
2500 #endif
2501 
2502 #endif	/* _EMLXS_HW_H */
2503