1 #ifndef IGU_DEFS_H 2 #define IGU_DEFS_H 3 4 #define IGU_FUNC_BASE 0x0400 5 6 #define IGU_ADDR_MSIX 0x0000 7 #define IGU_ADDR_INT_ACK 0x0200 8 #define IGU_ADDR_PROD_UPD 0x0201 9 #define IGU_ADDR_ATTN_BITS_UPD 0x0202 10 #define IGU_ADDR_ATTN_BITS_SET 0x0203 11 #define IGU_ADDR_ATTN_BITS_CLR 0x0204 12 #define IGU_ADDR_COALESCE_NOW 0x0205 13 #define IGU_ADDR_SIMD_MASK 0x0206 14 #define IGU_ADDR_SIMD_NOMASK 0x0207 15 #define IGU_ADDR_MSI_CTL 0x0210 16 #define IGU_ADDR_MSI_ADDR_LO 0x0211 17 #define IGU_ADDR_MSI_ADDR_HI 0x0212 18 #define IGU_ADDR_MSI_DATA 0x0213 19 20 21 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 22 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 23 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 24 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3 25 26 #define COMMAND_REG_INT_ACK 0x0 27 #define COMMAND_REG_PROD_UPD 0x4 28 #define COMMAND_REG_ATTN_BITS_UPD 0x8 29 #define COMMAND_REG_ATTN_BITS_SET 0xc 30 #define COMMAND_REG_ATTN_BITS_CLR 0x10 31 #define COMMAND_REG_COALESCE_NOW 0x14 32 #define COMMAND_REG_SIMD_MASK 0x18 33 #define COMMAND_REG_SIMD_NOMASK 0x1c 34 35 36 // Memory addresses on the BAR for the IGU Sub Block 37 #define IGU_MEM_BASE 0x0000 38 39 #define IGU_MEM_MSIX_BASE 0x0000 40 #define IGU_MEM_MSIX_UPPER 0x007f 41 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 42 43 #define IGU_MEM_PBA_MSIX_BASE 0x0200 44 #define IGU_MEM_PBA_MSIX_UPPER 0x0200 45 46 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 47 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 48 49 #define IGU_CMD_INT_ACK_BASE 0x0400 50 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PATH - 1) 51 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff 52 53 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500 54 #define IGU_CMD_E2_PROD_UPD_UPPER (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PATH - 1) 55 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f 56 57 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 58 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 59 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 60 61 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 62 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 63 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 64 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 65 66 67 #define IGU_REG_RESERVED_UPPER 0x05ff 68 69 #define IGU_SEG_IDX_ATTN 2 70 #define IGU_SEG_IDX_DEFAULT 1 71 /* Fields of IGU PF CONFIGRATION REGISTER */ 72 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 73 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 74 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 75 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 76 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 77 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 78 79 /* Fields of IGU VF CONFIGRATION REGISTER */ 80 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 81 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 82 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */ 83 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */ 84 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 85 86 87 #define IGU_BC_DSB_NUM_SEGS 5 88 #define IGU_BC_NDSB_NUM_SEGS 2 89 #define IGU_NORM_DSB_NUM_SEGS 2 90 #define IGU_NORM_NDSB_NUM_SEGS 1 91 #define IGU_BC_BASE_DSB_PROD 128 92 #define IGU_NORM_BASE_DSB_PROD 136 93 94 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; [5:2] = 0; [1:0] = PF number) */ 95 #define IGU_FID_ENCODE_IS_PF (0x1<<6) 96 #define IGU_FID_ENCODE_IS_PF_SHIFT 6 97 #define IGU_FID_VF_NUM_MASK (0x3f) 98 #define IGU_FID_PF_NUM_MASK (0x7) 99 100 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0) 101 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1) 102 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1 103 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7) 104 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7 105 106 #endif //IGU_DEFS_H 107 108