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Searched refs:HV_DRAM_CTL0 (Results 1 – 3 of 3) sorted by relevance

/titanic_41/usr/src/uts/sun4v/sys/
H A Dniagara2regs.h157 #define HV_DRAM_CTL0 0x1 macro
176 #define HV_DRAM_CTL0 0x2
208 #define HV_DRAM_CTL0 0x2
H A Dniagararegs.h100 #define HV_DRAM_CTL0 0x2 macro
/titanic_41/usr/src/uts/sun4v/cpu/
H A Dniagara_perfctr.c89 {HV_DRAM_CTL0, HV_DRAM_COUNT0},
94 {HV_DRAM_CTL0, HV_DRAM_COUNT0},