Searched refs:HC_R1INT_ENA (Results 1 – 2 of 2) sorted by relevance
608 #define EMLXS_MSI0_MASK2 (HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \610 #define EMLXS_MSI0_MASK1 (HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA| \672 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ macro
4450 if ((ha_copy2 & HA_R1ATT) && !(mask & HC_R1INT_ENA)) { in emlxs_get_attention()6655 (HC_R3INT_ENA | HC_R2INT_ENA | HC_R1INT_ENA | in emlxs_sli3_enable_intr()6658 status |= (HC_R2INT_ENA | HC_R1INT_ENA | HC_R0INT_ENA); in emlxs_sli3_enable_intr()6660 status |= (HC_R1INT_ENA | HC_R0INT_ENA); in emlxs_sli3_enable_intr()