| /titanic_41/usr/src/uts/common/io/afe/ |
| H A D | afeimpl.h | 289 #define GETCSR(afep, reg) \ macro
301 #define SETBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) | (val))
303 #define CLRBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) & ~(val))
|
| H A D | afe.c | 677 if ((GETCSR(afep, CSR_PAR) & PAR_RESET) == 0) { in afe_quiesce()
696 rxen = GETCSR(afep, CSR_NAR) & NAR_RX_ENABLE; in afe_setrxfilt()
889 val = GETCSR(afep, CSR_PAR); in afe_initialize()
931 (void) GETCSR(afep, CSR_LPC); in afe_initialize()
933 nar = GETCSR(afep, CSR_NAR); in afe_initialize()
976 if (!(GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT)) { in afe_sromwidth()
1035 if (GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT) { in afe_readsromword()
1178 bit = (GETCSR(afep, CSR_SPR) & SPR_MII_DIN) ? 1 : 0; in afe_miireadbit()
1458 if ((GETCSR(afep, CSR_SR) & (SR_TX_STATE | SR_RX_STATE)) == 0) in afe_stopmac()
1833 status = GETCSR(afep, CSR_SR2) & INT_ALL; in afe_intr()
[all …]
|
| /titanic_41/usr/src/uts/common/io/mxfe/ |
| H A D | mxfeimpl.h | 334 #define GETCSR(mxfep, reg) \ macro
341 PUTCSR(mxfep, reg, GETCSR(mxfep, reg) | (val))
344 PUTCSR(mxfep, reg, GETCSR(mxfep, reg) & ~(val))
|
| H A D | mxfe.c | 751 val = GETCSR(mxfep, CSR_PAR); in mxfe_initialize()
785 (void) GETCSR(mxfep, CSR_LPC); in mxfe_initialize()
788 nar = GETCSR(mxfep, CSR_NAR); in mxfe_initialize()
837 if (!(GETCSR(mxfep, CSR_SPR) & SPR_SROM_DOUT)) { in mxfe_sromwidth()
897 if (GETCSR(mxfep, CSR_SPR) & SPR_SROM_DOUT) { in mxfe_readsromword()
984 nar = GETCSR(mxfep, CSR_NAR); in mxfe_stopphy()
1025 nar = GETCSR(mxfep, CSR_NAR); in mxfe_startnway()
1035 tctl = GETCSR(mxfep, CSR_TCTL); in mxfe_startnway()
1081 tstat = GETCSR(mxfep, CSR_TSTAT); in mxfe_checklinknway()
1221 nar = GETCSR(mxfep, CSR_NAR); in mxfe_startphynway()
[all …]
|
| /titanic_41/usr/src/uts/common/io/efe/ |
| H A D | efe.h | 312 #define GETCSR(efep, reg) \ macro
321 PUTCSR(efep, reg, (GETCSR(efep, reg) & ~(bit)))
324 PUTCSR(efep, reg, (GETCSR(efep, reg) | (bit)))
|
| H A D | efe.c | 506 if (!(GETCSR(efep, CSR_MMCTL) & MMCTL_READ)) { in efe_mii_read()
507 return ((uint16_t)GETCSR(efep, CSR_MMDATA)); in efe_mii_read()
527 if (!(GETCSR(efep, CSR_MMCTL) & MMCTL_WRITE)) { in efe_mii_write()
885 status = GETCSR(efep, CSR_INTSTAT); in efe_intr()
1091 uint32_t status = GETCSR(efep, CSR_INTSTAT); in efe_stop_dma()
1587 addrlen = (GETCSR(efep, CSR_EECTL) & EECTL_SIZE ? in efe_eeprom_read()
1640 return (!!(GETCSR(efep, CSR_EECTL) & EECTL_EEDO)); in efe_eeprom_readbit()
|
| /titanic_41/usr/src/uts/common/sys/crypto/ |
| H A D | dca.h | 745 #define GETCSR(dca, reg) \ macro
752 PUTCSR(dca, reg, GETCSR(dca, reg) | val)
755 PUTCSR(dca, reg, GETCSR(dca, reg) & ~val)
|
| /titanic_41/usr/src/uts/common/crypto/io/ |
| H A D | dca.c | 762 DBG(dca, DCHATTY, "MCR1 = %x", GETCSR(dca, CSR_MCR1)); in dca_attach()
763 DBG(dca, DCHATTY, "CONTROL = %x", GETCSR(dca, CSR_DMACTL)); in dca_attach()
764 DBG(dca, DCHATTY, "STATUS = %x", GETCSR(dca, CSR_DMASTAT)); in dca_attach()
765 DBG(dca, DCHATTY, "DMAEA = %x", GETCSR(dca, CSR_DMAEA)); in dca_attach()
766 DBG(dca, DCHATTY, "MCR2 = %x", GETCSR(dca, CSR_MCR2)); in dca_attach()
1095 dmactl = GETCSR(dca, CSR_DMACTL); in dca_reset()
1389 status = GETCSR(dca, CSR_DMASTAT); in dca_intr()
1429 erraddr = GETCSR(dca, CSR_DMAEA); in dca_intr()
2173 status = GETCSR(dca, CSR_DMASTAT); in dca_schedule()
|