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Searched refs:FPGA_TP_ADDR_INTERRUPT_ENABLE (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dtp.c324 t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_ENABLE, in t1_tp_intr_enable()
345 t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_ENABLE, 0); in t1_tp_intr_disable()
H A Dfpga_defs.h47 #define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10 macro