xref: /titanic_41/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fc.h (revision d478d0a82b5f273f7eac89c8df47960d9d22820b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at
9  * http://www.opensource.org/licenses/cddl1.txt.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2004-2012 Emulex. All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _EMLXS_FC_H
28 #define	_EMLXS_FC_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 typedef struct emlxs_buf
35 {
36 	fc_packet_t		*pkt;		/* scsi_pkt reference */
37 	struct emlxs_port	*port;		/* pointer to port */
38 	void			*bmp;		/* Save the buffer pointer */
39 						/* list for later use. */
40 	struct emlxs_buf	*fc_fwd;	/* Use it by chip_Q */
41 	struct emlxs_buf	*fc_bkwd;	/* Use it by chip_Q */
42 	struct emlxs_buf	*next;		/* Use it when the iodone */
43 	struct emlxs_node 	*node;
44 	void			*channel;	/* Save channel and used by */
45 						/* abort */
46 	struct emlxs_buf	*fpkt;		/* Flush pkt pointer */
47 	struct XRIobj		*xrip;		/* Exchange resource */
48 	IOCBQ			iocbq;
49 	kmutex_t		mtx;
50 	uint32_t		pkt_flags;
51 	uint32_t		iotag;		/* iotag for this cmd */
52 	uint32_t		ticks;		/* save the timeout ticks */
53 						/* for the fc_packet_t */
54 	uint32_t		abort_attempts;
55 	uint32_t		lun;
56 #define	EMLXS_LUN_NONE		0xFFFFFFFF
57 
58 	uint32_t		class;		/* Save class and used by */
59 						/* abort */
60 	uint32_t		ucmd;		/* Unsolicted command that */
61 						/* this packet is responding */
62 						/* to, if any */
63 	int32_t			flush_count;	/* Valid only in flush pkts */
64 	uint32_t		did;
65 
66 #ifdef SFCT_SUPPORT
67 	kmutex_t		fct_mtx;
68 	fc_packet_t		*fct_pkt;
69 	fct_cmd_t		*fct_cmd;
70 
71 	uint8_t			fct_type;
72 
73 #define	EMLXS_FCT_ELS_CMD		0x01	/* Unsolicted */
74 #define	EMLXS_FCT_ELS_REQ		0x02	/* Solicited */
75 #define	EMLXS_FCT_ELS_RSP		0x04
76 #define	EMLXS_FCT_CT_REQ		0x08	/* Solicited */
77 #define	EMLXS_FCT_FCP_CMD		0x10	/* Unsolicted */
78 #define	EMLXS_FCT_FCP_DATA		0x20
79 #define	EMLXS_FCT_FCP_STATUS		0x40
80 
81 
82 	uint8_t			fct_flags;
83 
84 #define	EMLXS_FCT_SEND_STATUS		0x01
85 #define	EMLXS_FCT_ABORT_INP		0x02
86 #define	EMLXS_FCT_IO_INP		0x04
87 #define	EMLXS_FCT_PLOGI_RECEIVED	0x10
88 #define	EMLXS_FCT_REGISTERED		0x20
89 
90 	uint16_t		fct_state;
91 
92 #define	EMLXS_FCT_FCP_CMD_RECEIVED	1
93 #define	EMLXS_FCT_ELS_CMD_RECEIVED	2
94 #define	EMLXS_FCT_CMD_POSTED		3
95 #define	EMLXS_FCT_CMD_WAITQ		4
96 #define	EMLXS_FCT_SEND_CMD_RSP		5
97 #define	EMLXS_FCT_SEND_ELS_RSP		6
98 #define	EMLXS_FCT_SEND_ELS_REQ		7
99 #define	EMLXS_FCT_SEND_CT_REQ		8
100 #define	EMLXS_FCT_RSP_PENDING		9
101 #define	EMLXS_FCT_REQ_PENDING		10
102 #define	EMLXS_FCT_REG_PENDING		11
103 #define	EMLXS_FCT_REG_COMPLETE		12
104 #define	EMLXS_FCT_OWNED			13
105 #define	EMLXS_FCT_SEND_FCP_DATA		14
106 #define	EMLXS_FCT_SEND_FCP_STATUS	15
107 #define	EMLXS_FCT_DATA_PENDING		16
108 #define	EMLXS_FCT_STATUS_PENDING	17
109 #define	EMLXS_FCT_PKT_COMPLETE		18
110 #define	EMLXS_FCT_PKT_FCPRSP_COMPLETE	19
111 #define	EMLXS_FCT_PKT_ELSRSP_COMPLETE	20
112 #define	EMLXS_FCT_PKT_ELSCMD_COMPLETE	21
113 #define	EMLXS_FCT_PKT_CTCMD_COMPLETE	22
114 #define	EMLXS_FCT_REQ_COMPLETE		23
115 #define	EMLXS_FCT_CLOSE_PENDING		24
116 #define	EMLXS_FCT_ABORT_PENDING		25
117 #define	EMLXS_FCT_ABORT_DONE		26
118 #define	EMLXS_FCT_IO_DONE		27
119 
120 #define	EMLXS_FCT_IOCB_ISSUED		256 /* For tracing only */
121 #define	EMLXS_FCT_IOCB_COMPLETE		257 /* For tracing only */
122 
123 	stmf_data_buf_t		*fct_buf;
124 
125 #endif /* SFCT_SUPPORT */
126 
127 #ifdef SAN_DIAG_SUPPORT
128 	hrtime_t		sd_start_time;
129 #endif /* SAN_DIAG_SUPPORT */
130 
131 } emlxs_buf_t;
132 
133 
134 
135 #ifdef FCT_IO_TRACE
136 #define	EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state)	\
137 	(_cmd_sbp)->fct_state = _state;			\
138 	emlxs_fct_io_trace((_cmd_sbp)->port, _fct_cmd, _state)
139 #else
140 /* define to set fct_state */
141 #define	EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state)	\
142 	(_cmd_sbp)->fct_state = _state
143 #endif /* FCT_IO_TRACE */
144 
145 
146 /* pkt_flags */
147 #define	PACKET_IN_COMPLETION	0x00000001
148 #define	PACKET_IN_TXQ		0x00000002
149 #define	PACKET_IN_CHIPQ		0x00000004
150 #define	PACKET_IN_DONEQ		0x00000008
151 
152 #define	PACKET_FCP_RESET	0x00000030
153 #define	PACKET_FCP_TGT_RESET	0x00000010
154 #define	PACKET_FCP_LUN_RESET	0x00000020
155 #define	PACKET_POLLED		0x00000040
156 
157 #ifdef EMLXS_I386
158 #define	PACKET_FCP_SWAPPED	0x00000100
159 #define	PACKET_ELS_SWAPPED	0x00000200
160 #define	PACKET_CT_SWAPPED	0x00000400
161 #define	PACKET_CSP_SWAPPED	0x00000800
162 #endif	/* EMLXS_I386 */
163 
164 #define	PACKET_STALE		0x00001000
165 
166 #define	PACKET_IN_TIMEOUT	0x00010000
167 #define	PACKET_IN_FLUSH		0x00020000
168 #define	PACKET_IN_ABORT		0x00040000
169 #define	PACKET_XRI_CLOSED	0x00080000 /* An XRI abort/close was issued */
170 
171 #define	PACKET_CHIP_COMP	0x00100000
172 #define	PACKET_COMPLETED	0x00200000
173 #define	PACKET_ULP_OWNED	0x00400000
174 
175 #define	PACKET_STATE_VALID	0x01000000
176 #define	PACKET_FCP_RSP_VALID	0x02000000
177 #define	PACKET_ELS_RSP_VALID	0x04000000
178 #define	PACKET_CT_RSP_VALID	0x08000000
179 
180 #define	PACKET_DELAY_REQUIRED	0x10000000
181 #define	PACKET_ALLOCATED	0x40000000
182 #define	PACKET_VALID		0x80000000
183 
184 
185 #define	STALE_PACKET		((emlxs_buf_t *)0xFFFFFFFF)
186 
187 
188 /*
189  * From fc_error.h pkt_reason (except for state = NPORT_RJT, FABRIC_RJT,
190  * NPORT_BSY, FABRIC_BSY, LS_RJT, BA_RJT, FS_RJT)
191  *
192  * FCA unique error codes can begin after FC_REASON_FCA_UNIQUE.
193  * Each FCA defines its own set with values greater >= 0x7F
194  */
195 #define	FC_REASON_FCA_DEFINED   0x100
196 
197 
198 /*
199  * Device VPD save area
200  */
201 
202 typedef struct emlxs_vpd
203 {
204 	uint32_t	biuRev;
205 	uint32_t	smRev;
206 	uint32_t	smFwRev;
207 	uint32_t	endecRev;
208 	uint16_t	rBit;
209 	uint8_t		fcphHigh;
210 	uint8_t		fcphLow;
211 	uint8_t		feaLevelHigh;
212 	uint8_t		feaLevelLow;
213 
214 	uint32_t	postKernRev;
215 	char		postKernName[32];
216 
217 	uint32_t	opFwRev;
218 	char		opFwName[32];
219 	char		opFwLabel[32];
220 
221 	uint32_t	sli1FwRev;
222 	char		sli1FwName[32];
223 	char		sli1FwLabel[32];
224 
225 	uint32_t	sli2FwRev;
226 	char		sli2FwName[32];
227 	char		sli2FwLabel[32];
228 
229 	uint32_t	sli3FwRev;
230 	char		sli3FwName[32];
231 	char		sli3FwLabel[32];
232 
233 	uint32_t	sli4FwRev;
234 	char		sli4FwName[32];
235 	char		sli4FwLabel[32];
236 
237 	char		fw_version[32];
238 	char		fw_label[32];
239 
240 	char		fcode_version[32];
241 	char		boot_version[32];
242 
243 	char		serial_num[32];
244 	char		part_num[32];
245 	char		port_num[20];
246 	char		eng_change[32];
247 	char		manufacturer[80];
248 	char		model[80];
249 	char		model_desc[256];
250 	char		prog_types[256];
251 	char		id[256];
252 
253 	uint32_t	port_index;
254 	uint16_t	link_speed;
255 } emlxs_vpd_t;
256 
257 
258 typedef struct emlxs_queue
259 {
260 	void		*q_first;	/* queue first element */
261 	void		*q_last;	/* queue last element */
262 	uint16_t	q_cnt;	/* current length of queue */
263 	uint16_t	q_max;	/* max length queue can get */
264 } emlxs_queue_t;
265 typedef emlxs_queue_t Q;
266 
267 
268 
269 /*
270  * This structure is used when allocating a buffer pool.
271  * Note: this should be identical to gasket buf_info (fldl.h).
272  */
273 typedef struct emlxs_buf_info
274 {
275 	int32_t		size;	/* Specifies the number of bytes to allocate. */
276 	int32_t		align;	/* The desired address boundary. */
277 
278 	int32_t		flags;
279 
280 #define	FC_MBUF_DMA		0x01	/* blocks are for DMA */
281 #define	FC_MBUF_PHYSONLY	0x02	/* For malloc - map a given virtual */
282 					/* address to physical address (skip */
283 					/* the malloc). */
284 					/* For free - just unmap the given */
285 					/* physical address (skip the free). */
286 #define	FC_MBUF_IOCTL		0x04	/* called from dfc_ioctl */
287 #define	FC_MBUF_UNLOCK		0x08	/* called with driver unlocked */
288 #define	FC_MBUF_SNGLSG		0x10	/* allocate a single contiguous */
289 					/* physical memory */
290 #define	FC_MBUF_DMA32		0x20
291 
292 	uint64_t	phys;		/* specifies physical buffer pointer */
293 	void		*virt;		/* specifies virtual buffer pointer */
294 	void		*data_handle;
295 	void		*dma_handle;
296 } emlxs_buf_info_t;
297 typedef emlxs_buf_info_t MBUF_INFO;
298 
299 
300 #define	EMLXS_MAX_HBQ   	16	/* Max HBQs handled by firmware */
301 #define	EMLXS_ELS_HBQ_ID	0
302 #define	EMLXS_IP_HBQ_ID		1
303 #define	EMLXS_CT_HBQ_ID		2
304 #define	EMLXS_FCT_HBQ_ID	3
305 
306 #ifdef SFCT_SUPPORT
307 #define	EMLXS_NUM_HBQ		4	/* Number of HBQs supported by driver */
308 #else
309 #define	EMLXS_NUM_HBQ		3	/* Number of HBQs supported by driver */
310 #endif /* SFCT_SUPPORT */
311 
312 
313 /*
314  * An IO Channel is a object that comprises a xmit/cmpl
315  * path for IOs.
316  * For SLI3, an IO path maps to a ring (cmd/rsp)
317  * For SLI4, an IO path map to a queue pair (WQ/CQ)
318  */
319 typedef struct emlxs_channel
320 {
321 	struct emlxs_hba *hba;			/* ptr to hba for channel */
322 	void		*iopath;		/* ptr to SLI3/4 io path */
323 
324 	kmutex_t	rsp_lock;
325 	IOCBQ		*rsp_head;	/* deferred completion head */
326 	IOCBQ		*rsp_tail;	/* deferred completion tail */
327 	emlxs_thread_t  intr_thread;
328 
329 
330 	uint16_t	channelno;
331 	uint16_t	chan_flag;
332 
333 #define	EMLXS_NEEDS_TRIGGER 1
334 
335 	/* Protected by EMLXS_TX_CHANNEL_LOCK */
336 	emlxs_queue_t	nodeq;			/* Node service queue */
337 
338 	kmutex_t	channel_cmd_lock;
339 	uint32_t	timeout;
340 
341 	/* Channel command counters */
342 	uint32_t	ulpSendCmd;
343 	uint32_t	ulpCmplCmd;
344 	uint32_t	hbaSendCmd;
345 	uint32_t	hbaCmplCmd;
346 	uint32_t	hbaSendCmd_sbp;
347 	uint32_t	hbaCmplCmd_sbp;
348 
349 } emlxs_channel_t;
350 typedef emlxs_channel_t CHANNEL;
351 
352 /*
353  * Should be able to handle max number of io paths for a
354  * SLI4 HBA (EMLXS_MAX_WQS) or for a SLI3 HBA (MAX_RINGS)
355  */
356 #define	MAX_CHANNEL EMLXS_MSI_MAX_INTRS
357 
358 
359 /* Structure used to access adapter rings */
360 typedef struct emlxs_ring
361 {
362 	void		*fc_cmdringaddr;	/* virtual offset for cmd */
363 						/* rings */
364 	void		*fc_rspringaddr;	/* virtual offset for rsp */
365 						/* rings */
366 
367 	void		*fc_mpon;		/* index ptr for match */
368 						/* structure */
369 	void		*fc_mpoff;		/* index ptr for match */
370 						/* structure */
371 	struct emlxs_hba *hba;			/* ptr to hba for ring */
372 
373 	uint8_t		fc_numCiocb;		/* number of command iocb's */
374 						/* per ring */
375 	uint8_t		fc_numRiocb;		/* number of response iocb's */
376 						/* per ring */
377 	uint8_t		fc_rspidx;		/* current index in response */
378 						/* ring */
379 	uint8_t		fc_cmdidx;		/* current index in command */
380 						/* ring */
381 	uint8_t		fc_port_rspidx;
382 	uint8_t		fc_port_cmdidx;
383 	uint8_t		ringno;
384 
385 	uint16_t	fc_missbufcnt;		/* buf cnt we need to repost */
386 	CHANNEL		*channelp;
387 
388 
389 } emlxs_ring_t;
390 typedef emlxs_ring_t RING;
391 
392 
393 #ifdef SAN_DIAG_SUPPORT
394 /*
395  * Although right now it's just 1 field, SAN Diag anticipates that this
396  * structure will grow in the future.
397  */
398 typedef struct sd_timestat_level0 {
399 	int		count;
400 } sd_timestat_level0_t;
401 #endif
402 
403 typedef struct emlxs_node
404 {
405 	struct emlxs_node	*nlp_list_next;
406 	struct emlxs_node	*nlp_list_prev;
407 
408 	NAME_TYPE		nlp_portname;	/* port name */
409 	NAME_TYPE		nlp_nodename;	/* node name */
410 
411 	uint32_t		nlp_DID;	/* fibre channel D_ID */
412 
413 	uint16_t		nlp_Rpi;	/* login id returned by */
414 						/* REG_LOGIN */
415 	uint16_t		nlp_Xri;	/* login id returned by */
416 						/* REG_LOGIN */
417 
418 	uint8_t			nlp_fcp_info;	/* Remote class info */
419 
420 	/* nlp_fcp_info */
421 #define	NLP_FCP_TGT_DEVICE	0x10	/* FCP TGT device */
422 #define	NLP_FCP_INI_DEVICE	0x20	/* FCP Initiator device */
423 #define	NLP_FCP_2_DEVICE	0x40	/* FCP-2 TGT device */
424 #define	NLP_EMLX_VPORT		0x80    /* Virtual port */
425 
426 	uint8_t			dfc_state;
427 #define	EMLXS_SET_DFC_STATE(_n, _state)	if (_n && _n->nlp_active)\
428 		{(_n)->dfc_state = (_state); }
429 
430 	uint32_t		nlp_force_rscn;
431 	uint32_t		nlp_tag;	/* Tag used by port_offline */
432 	uint32_t		flag;
433 
434 #define	NODE_POOL_ALLOCATED 	0x00000001
435 
436 	SERV_PARM		sparm;
437 
438 	/* Protected by EMLXS_TX_CHANNEL_LOCK */
439 	uint32_t		nlp_active;	/* Node active flag */
440 	uint32_t		nlp_base;
441 	uint32_t		nlp_flag[MAX_CHANNEL];	/* Node level channel */
442 							/* flags */
443 
444 	/* nlp_flag */
445 #define	NLP_CLOSED		0x1
446 #define	NLP_OFFLINE		0x2
447 #define	NLP_RPI_XRI		0x4
448 
449 	uint32_t		nlp_tics[MAX_CHANNEL];	/* gate timeout */
450 	emlxs_queue_t		nlp_tx[MAX_CHANNEL];	/* Transmit Q head */
451 	emlxs_queue_t		nlp_ptx[MAX_CHANNEL];	/* Priority transmit */
452 							/* Queue head */
453 	void			*nlp_next[MAX_CHANNEL];	/* Service Request */
454 							/* Queue pointer used */
455 							/* when node needs */
456 							/* servicing */
457 #ifdef DHCHAP_SUPPORT
458 	emlxs_node_dhc_t	node_dhc;
459 #endif	/* DHCHAP_SUPPORT */
460 
461 #ifdef SAN_DIAG_SUPPORT
462 	sd_timestat_level0_t	sd_dev_bucket[SD_IO_LATENCY_MAX_BUCKETS];
463 #endif
464 
465 	struct RPIobj		*rpip;	/* SLI4 only */
466 #define	EMLXS_NODE_TO_RPI(_p, _n)	\
467 	((_n)?((_n->rpip)?_n->rpip:emlxs_rpi_find(_p, _n->nlp_Rpi)):NULL)
468 
469 #ifdef NODE_THROTTLE_SUPPORT
470 	uint32_t io_throttle;
471 	uint32_t io_active;
472 #endif /* NODE_THROTTLE_SUPPORT */
473 
474 } emlxs_node_t;
475 typedef emlxs_node_t NODELIST;
476 
477 
478 
479 #define	NADDR_LEN	6	/* MAC network address length */
480 typedef struct emlxs_fcip_nethdr
481 {
482 	NAME_TYPE	fc_destname;	/* destination port name */
483 	NAME_TYPE	fc_srcname;	/* source port name */
484 } emlxs_fcip_nethdr_t;
485 typedef emlxs_fcip_nethdr_t NETHDR;
486 
487 
488 #define	MEM_NLP		0	/* memory segment to hold node list entries */
489 #define	MEM_IOCB	1	/* memory segment to hold iocb commands */
490 #define	MEM_MBOX	2	/* memory segment to hold mailbox cmds  */
491 #define	MEM_BPL		3	/* and to hold buffer ptr lists - SLI2   */
492 #define	MEM_BUF		4	/* memory segment to hold buffer data   */
493 #define	MEM_ELSBUF	4	/* memory segment to hold buffer data   */
494 #define	MEM_IPBUF	5	/* memory segment to hold IP buffer data */
495 #define	MEM_CTBUF	6	/* memory segment to hold CT buffer data */
496 #define	MEM_FCTBUF	7	/* memory segment to hold FCT buffer data */
497 
498 #ifdef SFCT_SUPPORT
499 #define	FC_MAX_SEG	8
500 #define	MEM_FCTSEG	10 /* must be greater than FC_MAX_SEG */
501 #else
502 #define	FC_MAX_SEG	7
503 #endif /* SFCT_SUPPORT */
504 
505 
506 /* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */
507 #define	BPL_TO_SGLLEN(_bpl)	((_bpl/12)-2)
508 #define	MEM_BPL_SIZE		36 /* Default size */
509 
510 /* A SGL entry is 16 bytes. Subtract 2 for command and response buffers */
511 #define	SGL_TO_SGLLEN(_sgl)	((_sgl/16)-2)
512 #define	MEM_SGL_SIZE		4096 /* Default size */
513 
514 #define	MEM_BUF_SIZE		1024
515 #define	MEM_BUF_COUNT		64
516 
517 #define	MEM_ELSBUF_SIZE   	MEM_BUF_SIZE
518 #define	MEM_ELSBUF_COUNT  	hba->max_nodes
519 #define	MEM_IPBUF_SIZE  	65535
520 #define	MEM_IPBUF_COUNT		60
521 #define	MEM_CTBUF_SIZE		MAX_CT_PAYLOAD	/* (1024*320) */
522 #define	MEM_CTBUF_COUNT		8
523 #define	MEM_FCTBUF_SIZE  	65535
524 #define	MEM_FCTBUF_COUNT	128
525 
526 typedef struct emlxs_memseg
527 {
528 	void			*fc_memget_ptr;
529 	void			*fc_memget_end;
530 	void			*fc_memput_ptr;
531 	void			*fc_memput_end;
532 
533 	uint32_t		fc_total_memsize;
534 	uint32_t		fc_memsize;		/* size of mem blks */
535 	uint32_t		fc_numblks;		/* no of mem blks */
536 	uint32_t		fc_memget_cnt;		/* no of mem get blks */
537 	uint32_t		fc_memput_cnt;		/* no of mem put blks */
538 	uint32_t		fc_memflag;  /* emlxs_buf_info_t FLAGS */
539 #define	FC_MEMSEG_PUT_ENABLED	0x20000000
540 #define	FC_MEMSEG_GET_ENABLED	0x40000000
541 #define	FC_MEMSEG_DYNAMIC	0x80000000
542 
543 	uint32_t		fc_memalign;
544 	uint32_t		fc_memtag;
545 	char			fc_label[32];
546 
547 	uint32_t		fc_hi_water;
548 	uint32_t		fc_lo_water;
549 	uint32_t		fc_step;  /* Dyn increment.  Zero = static */
550 	uint32_t		fc_low;   /* Lowest free count (dyn only) */
551 	uint32_t		fc_last;  /* Last fc_numblks (dyn only) */
552 
553 } emlxs_memseg_t;
554 typedef emlxs_memseg_t MEMSEG;
555 
556 
557 /* Board stat counters */
558 typedef struct emlxs_stats
559 {
560 	uint32_t	LinkUp;
561 	uint32_t	LinkDown;
562 	uint32_t	LinkEvent;
563 	uint32_t	LinkMultiEvent;
564 
565 	uint32_t	MboxIssued;
566 	uint32_t	MboxCompleted;	/* MboxError + MbxGood */
567 	uint32_t	MboxGood;
568 	uint32_t	MboxError;
569 	uint32_t	MboxBusy;
570 	uint32_t	MboxInvalid;
571 
572 	uint32_t	IocbIssued[MAX_CHANNEL];
573 	uint32_t	IocbReceived[MAX_CHANNEL];
574 	uint32_t	IocbTxPut[MAX_CHANNEL];
575 	uint32_t	IocbTxGet[MAX_CHANNEL];
576 	uint32_t	IocbRingFull[MAX_CHANNEL];
577 	uint32_t	IocbThrottled;
578 
579 	uint32_t	IntrEvent[8];
580 
581 	uint32_t	FcpIssued;
582 	uint32_t	FcpCompleted;	/* FcpGood + FcpError */
583 	uint32_t	FcpGood;
584 	uint32_t	FcpError;
585 
586 	uint32_t	FcpEvent;	/* FcpStray + FcpCompleted */
587 	uint32_t	FcpStray;
588 #ifdef SFCT_SUPPORT
589 	uint32_t	FctRingEvent;
590 	uint32_t	FctRingError;
591 	uint32_t	FctRingDropped;
592 #endif /* SFCT_SUPPORT */
593 
594 	uint32_t	ElsEvent;	/* ElsStray + ElsCmplt (cmd + rsp) */
595 	uint32_t	ElsStray;
596 
597 	uint32_t	ElsCmdIssued;
598 	uint32_t	ElsCmdCompleted;	/* ElsCmdGood + ElsCmdError */
599 	uint32_t	ElsCmdGood;
600 	uint32_t	ElsCmdError;
601 
602 	uint32_t	ElsRspIssued;
603 	uint32_t	ElsRspCompleted;
604 
605 	uint32_t	ElsRcvEvent;	/* ElsRcvErr + ElsRcvDrop + ElsCmdRcv */
606 	uint32_t	ElsRcvError;
607 	uint32_t	ElsRcvDropped;
608 	uint32_t	ElsCmdReceived;	/* ElsRscnRcv + ElsPlogiRcv + ... */
609 	uint32_t	ElsRscnReceived;
610 	uint32_t	ElsFlogiReceived;
611 	uint32_t	ElsPlogiReceived;
612 	uint32_t	ElsPrliReceived;
613 	uint32_t	ElsPrloReceived;
614 	uint32_t	ElsLogoReceived;
615 	uint32_t	ElsAdiscReceived;
616 	uint32_t	ElsAuthReceived;
617 	uint32_t	ElsGenReceived;
618 
619 	uint32_t	CtEvent;	/* CtStray + CtCompleted (cmd + rsp) */
620 	uint32_t	CtStray;
621 
622 	uint32_t	CtCmdIssued;
623 	uint32_t	CtCmdCompleted;	/* CtCmdGood + CtCmdError */
624 	uint32_t	CtCmdGood;
625 	uint32_t	CtCmdError;
626 
627 	uint32_t	CtRspIssued;
628 	uint32_t	CtRspCompleted;
629 
630 	uint32_t	CtRcvEvent;	/* CtRcvError + CtRcvDrop + CtCmdRcvd */
631 	uint32_t	CtRcvError;
632 	uint32_t	CtRcvDropped;
633 	uint32_t	CtCmdReceived;
634 
635 	uint32_t	IpEvent;	/* IpStray + IpSeqCmpl + IpBcastCmpl */
636 	uint32_t	IpStray;
637 
638 	uint32_t	IpSeqIssued;
639 	uint32_t	IpSeqCompleted;	/* IpSeqGood + IpSeqError */
640 	uint32_t	IpSeqGood;
641 	uint32_t	IpSeqError;
642 
643 	uint32_t	IpBcastIssued;
644 	uint32_t	IpBcastCompleted;	/* IpBcastGood + IpBcastError */
645 	uint32_t	IpBcastGood;
646 	uint32_t	IpBcastError;
647 
648 	uint32_t	IpRcvEvent;	/* IpDrop + IpSeqRcv + IpBcastRcv */
649 	uint32_t	IpDropped;
650 	uint32_t	IpSeqReceived;
651 	uint32_t	IpBcastReceived;
652 
653 	uint32_t	IpUbPosted;
654 	uint32_t	ElsUbPosted;
655 	uint32_t	CtUbPosted;
656 #ifdef SFCT_SUPPORT
657 	uint32_t	FctUbPosted;
658 #endif /* SFCT_SUPPORT */
659 
660 	uint32_t	ResetTime;	/* Time of last reset */
661 
662 	uint32_t	ElsTestReceived;
663 	uint32_t	ElsEstcReceived;
664 	uint32_t	ElsFarprReceived;
665 	uint32_t	ElsEchoReceived;
666 	uint32_t	ElsRlsReceived;
667 	uint32_t	ElsRtvReceived;
668 
669 } emlxs_stats_t;
670 
671 
672 #define	FC_MAX_ADPTMSG   (8*28)	/* max size of a msg from adapter */
673 
674 #define	EMLXS_NUM_THREADS	8
675 #define	EMLXS_MIN_TASKS		8
676 #define	EMLXS_MAX_TASKS		8
677 
678 #define	EMLXS_NUM_HASH_QUES	32
679 #define	EMLXS_DID_HASH(x)	((x) & (EMLXS_NUM_HASH_QUES - 1))
680 
681 
682 /* pkt_tran_flag */
683 #define	FC_TRAN_COMPLETED	0x8000
684 
685 
686 typedef struct emlxs_dfc_event
687 {
688 	uint32_t	pid;
689 	uint32_t	event;
690 	uint32_t	last_id;
691 
692 	void		*dataout;
693 	uint32_t	size;
694 	uint32_t	mode;
695 } emlxs_dfc_event_t;
696 
697 
698 typedef struct emlxs_hba_event
699 {
700 	uint32_t	last_id;
701 	uint32_t	new;
702 	uint32_t	missed;
703 } emlxs_hba_event_t;
704 
705 
706 #ifdef SFCT_SUPPORT
707 
708 #define	TGTPORTSTAT			port->fct_stat
709 
710 /*
711  * FctP2IOXcnt will count IOs by their fcpDL. Counters
712  * are for buckets of various power of 2 sizes.
713  * Bucket 0  <  512  > 0
714  * Bucket 1  >= 512  < 1024
715  * Bucket 2  >= 1024 < 2048
716  * Bucket 3  >= 2048 < 4096
717  * Bucket 4  >= 4096 < 8192
718  * Bucket 5  >= 8192 < 16K
719  * Bucket 6  >= 16K  < 32K
720  * Bucket 7  >= 32K  < 64K
721  * Bucket 8  >= 64K  < 128K
722  * Bucket 9  >= 128K < 256K
723  * Bucket 10 >= 256K < 512K
724  * Bucket 11 >= 512K < 1MB
725  * Bucket 12 >= 1MB  < 2MB
726  * Bucket 13 >= 2MB  < 4MB
727  * Bucket 14 >= 4MB  < 8MB
728  * Bucket 15 >= 8MB
729  */
730 #define	MAX_TGTPORT_IOCNT  16
731 
732 
733 /*
734  * These routines will bump the right counter, based on
735  * the size of the IO inputed, with the least number of
736  * comparisions.  A max of 5 comparisions is only needed
737  * to classify the IO in one of 16 ranges. A binary search
738  * to locate the high bit in the size is used.
739  */
740 #define	EMLXS_BUMP_RDIOCTR(port, cnt) \
741 { \
742 	/* Use binary search to find the first high bit */ \
743 	if (cnt & 0xffff0000) { \
744 		if (cnt & 0xff800000) { \
745 			TGTPORTSTAT.FctP2IORcnt[15]++; \
746 		} \
747 		else { \
748 			/* It must be 0x007f0000 */ \
749 			if (cnt & 0x00700000) { \
750 				if (cnt & 0x00400000) { \
751 					TGTPORTSTAT.FctP2IORcnt[14]++; \
752 				} \
753 				else { \
754 					/* it must be 0x00300000 */ \
755 					if (cnt & 0x00200000) { \
756 						TGTPORTSTAT.FctP2IORcnt[13]++; \
757 					} \
758 					else { \
759 						/* It must be 0x00100000 */ \
760 						TGTPORTSTAT.FctP2IORcnt[12]++; \
761 					} \
762 				} \
763 			} \
764 			else { \
765 				/* It must be 0x000f0000 */ \
766 				if (cnt & 0x000c0000) {	\
767 					if (cnt & 0x00080000) {	\
768 						TGTPORTSTAT.FctP2IORcnt[11]++; \
769 					} \
770 					else { \
771 						/* It must be 0x00040000 */ \
772 						TGTPORTSTAT.FctP2IORcnt[10]++; \
773 					} \
774 				} \
775 				else { \
776 					/* It must be 0x00030000 */ \
777 					if (cnt & 0x00020000) {	\
778 						TGTPORTSTAT.FctP2IORcnt[9]++; \
779 					} \
780 					else { \
781 						/* It must be 0x00010000 */ \
782 						TGTPORTSTAT.FctP2IORcnt[8]++; \
783 					} \
784 				} \
785 			} \
786 		} \
787 	} \
788 	else { \
789 		if (cnt & 0x0000fe00) { \
790 			if (cnt & 0x0000f000) { \
791 				if (cnt & 0x0000c000) { \
792 					if (cnt & 0x00008000) { \
793 						TGTPORTSTAT.FctP2IORcnt[7]++; \
794 					} \
795 					else { \
796 						/* It must be 0x00004000 */ \
797 						TGTPORTSTAT.FctP2IORcnt[6]++; \
798 					} \
799 				} \
800 				else { \
801 					/* It must be 0x00000300 */ \
802 					if (cnt & 0x00000200) { \
803 						TGTPORTSTAT.FctP2IORcnt[5]++; \
804 					} \
805 					else { \
806 						/* It must be 0x00000100 */ \
807 						TGTPORTSTAT.FctP2IORcnt[4]++; \
808 					} \
809 				} \
810 			} \
811 			else { \
812 				/* It must be 0x00000e00 */ \
813 				if (cnt & 0x00000800) { \
814 					TGTPORTSTAT.FctP2IORcnt[3]++; \
815 				} \
816 				else { \
817 					/* It must be 0x00000600 */ \
818 					if (cnt & 0x00000400) { \
819 						TGTPORTSTAT.FctP2IORcnt[2]++; \
820 					} \
821 					else { \
822 						/* It must be 0x00000200 */ \
823 						TGTPORTSTAT.FctP2IORcnt[1]++; \
824 					} \
825 				} \
826 			} \
827 		} \
828 		else { \
829 			/* It must be 0x000001ff */ \
830 			TGTPORTSTAT.FctP2IORcnt[0]++; \
831 		} \
832 	} \
833 }
834 
835 
836 #define	EMLXS_BUMP_WRIOCTR(port, cnt) \
837 { \
838 /* Use binary search to find the first high bit */ \
839 	if (cnt & 0xffff0000) { \
840 		if (cnt & 0xff800000) { \
841 			TGTPORTSTAT.FctP2IOWcnt[15]++; \
842 		} \
843 		else { \
844 			/* It must be 0x007f0000 */ \
845 			if (cnt & 0x00700000) { \
846 				if (cnt & 0x00400000) { \
847 					TGTPORTSTAT.FctP2IOWcnt[14]++; \
848 				} \
849 				else { \
850 					/* It must be 0x00300000 */ \
851 					if (cnt & 0x00200000) { \
852 						TGTPORTSTAT.FctP2IOWcnt[13]++; \
853 					} \
854 					else { \
855 						/* It must be 0x00100000 */ \
856 						TGTPORTSTAT.FctP2IOWcnt[12]++; \
857 					} \
858 				} \
859 			} \
860 			else { \
861 				/* It must be 0x000f0000 */ \
862 				if (cnt & 0x000c0000) { \
863 					if (cnt & 0x00080000) { \
864 						TGTPORTSTAT.FctP2IOWcnt[11]++; \
865 					} \
866 					else { \
867 						/* it must be 0x00040000 */ \
868 						TGTPORTSTAT.FctP2IOWcnt[10]++; \
869 					} \
870 				} \
871 				else { \
872 					/* It must be 0x00030000 */ \
873 					if (cnt & 0x00020000) { \
874 						TGTPORTSTAT.FctP2IOWcnt[9]++; \
875 					} \
876 					else { \
877 						/* It must be 0x00010000 */ \
878 						TGTPORTSTAT.FctP2IOWcnt[8]++; \
879 					} \
880 				} \
881 			} \
882 		} \
883 	} \
884 	else { \
885 		if (cnt & 0x0000fe00) { \
886 			if (cnt & 0x0000f000) { \
887 				if (cnt & 0x0000c000) { \
888 					if (cnt & 0x00008000) { \
889 						TGTPORTSTAT.FctP2IOWcnt[7]++; \
890 					} \
891 					else { \
892 						/* It must be 0x00004000 */ \
893 						TGTPORTSTAT.FctP2IOWcnt[6]++; \
894 					} \
895 				} \
896 				else { \
897 					/* It must be 0x00000300 */ \
898 					if (cnt & 0x00000200) { \
899 						TGTPORTSTAT.FctP2IOWcnt[5]++; \
900 					} \
901 					else { \
902 						/* It must be 0x00000100 */ \
903 						TGTPORTSTAT.FctP2IOWcnt[4]++; \
904 					} \
905 				} \
906 			} \
907 			else { \
908 				/* It must be 0x00000e00 */ \
909 				if (cnt & 0x00000800) { \
910 					TGTPORTSTAT.FctP2IOWcnt[3]++; \
911 				} \
912 				else { \
913 					/* It must be 0x00000600 */ \
914 					if (cnt & 0x00000400) { \
915 						TGTPORTSTAT.FctP2IOWcnt[2]++; \
916 					} \
917 					else { \
918 						/* It must be 0x00000200 */ \
919 						TGTPORTSTAT.FctP2IOWcnt[1]++; \
920 					} \
921 				} \
922 			} \
923 		} \
924 		else { \
925 			/* It must be 0x000001ff */ \
926 			TGTPORTSTAT.FctP2IOWcnt[0]++; \
927 		} \
928 	} \
929 }
930 
931 typedef struct emlxs_tgtport_stat
932 {
933 	/* IO counters */
934 	uint64_t	FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */
935 	uint64_t	FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads  */
936 	uint64_t	FctIOCmdCnt;			/* Other, ie TUR */
937 	uint64_t	FctCmdReceived;			/* total IOs */
938 	uint64_t	FctReadBytes;			/* total read bytes */
939 	uint64_t	FctWriteBytes;			/* total write bytes */
940 
941 	/* IOCB handling counters */
942 	uint64_t	FctEvent;	/* FctStray + FctCompleted */
943 	uint64_t	FctCompleted;	/* FctCmplGood + FctCmplError */
944 	uint64_t	FctCmplGood;
945 
946 	uint32_t	FctCmplError;
947 	uint32_t	FctStray;
948 
949 	/* Fct event counters */
950 	uint32_t	FctRcvDropped;
951 	uint32_t	FctOverQDepth;
952 	uint32_t	FctOutstandingIO;
953 	uint32_t	FctFailedPortRegister;
954 	uint32_t	FctPortRegister;
955 	uint32_t	FctPortDeregister;
956 
957 	uint32_t	FctAbortSent;
958 	uint32_t	FctNoBuffer;
959 	uint32_t	FctScsiStatusErr;
960 	uint32_t	FctScsiQfullErr;
961 	uint32_t	FctScsiResidOver;
962 	uint32_t	FctScsiResidUnder;
963 	uint32_t	FctScsiSenseErr;
964 
965 	uint32_t	FctFiller1;
966 } emlxs_tgtport_stat_t;
967 
968 #ifdef FCT_IO_TRACE
969 #define	MAX_IO_TRACE	67
970 typedef struct emlxs_iotrace
971 {
972 	fct_cmd_t	*fct_cmd;
973 	uint32_t	xri;
974 	uint8_t		marker;  /* 0xff */
975 	uint8_t		trc[MAX_IO_TRACE]; /* trc[0] = index */
976 } emlxs_iotrace_t;
977 #endif /* FCT_IO_TRACE */
978 #endif /* SFCT_SUPPORT */
979 
980 
981 #include <emlxs_fcf.h>
982 
983 /*
984  *     Port Information Data Structure
985  */
986 
987 typedef struct emlxs_port
988 {
989 	struct emlxs_hba	*hba;
990 
991 	/* Virtual port management */
992 	struct VPIobj		VPIobj;
993 	struct VPIobj		*vpip; /* &VPIobj */
994 
995 	uint32_t		vpi;	/* Legacy vpi == vpip->index */
996 	uint32_t		mode;
997 	uint32_t		mode_mask; /* User configured */
998 #define	MODE_NONE			0x00000000
999 #define	MODE_INITIATOR			0x00000001
1000 #define	MODE_TARGET			0x00000002
1001 #define	MODE_ALL			0x00000003
1002 
1003 	uint32_t		flag;
1004 #define	EMLXS_PORT_ENABLED		0x00000001 /* vport setting */
1005 #define	EMLXS_PORT_CONFIG		0x00000002 /* vport setting */
1006 
1007 #define	EMLXS_INI_ENABLED		0x00000010 /* emlxs_mode_init */
1008 #define	EMLXS_INI_BOUND			0x00000020 /* emlxs_fca_bind_port */
1009 #define	EMLXS_TGT_ENABLED		0x00000040 /* emlxs_mode_init */
1010 #define	EMLXS_TGT_BOUND			0x00000080 /* emlxs_fct_bind_port */
1011 #define	EMLXS_PORT_BOUND		(EMLXS_INI_BOUND|EMLXS_TGT_BOUND)
1012 
1013 #define	EMLXS_PORT_IP_UP		0x00000100
1014 #define	EMLXS_PORT_RESTRICTED		0x00000200 /* Restrict logins */
1015 
1016 #define	EMLXS_PORT_REG_VPI		0x00010000 /* SLI3 */
1017 #define	EMLXS_PORT_REG_VPI_CMPL		0x00020000 /* SLI3 */
1018 
1019 #define	EMLXS_PORT_FLOGI_CMPL		0x01000000	/* Fabric login */
1020 							/* completed */
1021 
1022 #define	EMLXS_PORT_RESET_MASK		0x0000FFFF	/* Flags to keep */
1023 							/* across hard reset */
1024 #define	EMLXS_PORT_LINKDOWN_MASK	0x00FFFFFF	/* Flags to keep */
1025 							/* across link reset */
1026 
1027 	uint32_t		options;
1028 #define	EMLXS_OPT_RESTRICT		0x00000001 /* Force restricted */
1029 						/* logins */
1030 #define	EMLXS_OPT_UNRESTRICT		0x00000002 /* Force Unrestricted */
1031 						/* logins */
1032 #define	EMLXS_OPT_RESTRICT_MASK		0x00000003
1033 
1034 
1035 	/* FC world wide names */
1036 	NAME_TYPE		wwnn;
1037 	NAME_TYPE		wwpn;
1038 	char			snn[256];
1039 	char			spn[256];
1040 
1041 	/* Common service paramters */
1042 	SERV_PARM		sparam;
1043 	SERV_PARM		fabric_sparam;
1044 	SERV_PARM		prev_fabric_sparam;
1045 
1046 	/* fc_id management */
1047 	uint32_t		did;
1048 	uint32_t		prev_did;
1049 
1050 	/* support FC_PORT_GET_P2P_INFO only */
1051 	uint32_t		rdid;
1052 
1053 	/* FC_AL management */
1054 	uint8_t			lip_type;
1055 	uint8_t			granted_alpa;
1056 	uint8_t			alpa_map[128];
1057 
1058 	/* Node management */
1059 	emlxs_node_t		node_base;
1060 	uint32_t		node_count;
1061 	krwlock_t		node_rwlock;
1062 	emlxs_node_t		*node_table[EMLXS_NUM_HASH_QUES];
1063 
1064 	/* Polled packet management */
1065 	kcondvar_t		pkt_lock_cv;	/* pkt polling */
1066 	kmutex_t		pkt_lock;	/* pkt polling */
1067 
1068 	/* ULP */
1069 	uint32_t		ulp_busy;
1070 	uint32_t		ulp_statec;
1071 	void			(*ulp_statec_cb) ();	/* Port state change */
1072 							/* callback routine */
1073 	void			(*ulp_unsol_cb) ();	/* unsolicited event */
1074 							/* callback routine */
1075 	opaque_t		ulp_handle;
1076 
1077 	/* ULP unsolicited buffers */
1078 	kmutex_t		ub_lock;
1079 	uint32_t		ub_count;
1080 	emlxs_unsol_buf_t	*ub_pool;
1081 	uint32_t		ub_post[MAX_CHANNEL];
1082 	uint32_t		ub_timer;
1083 
1084 	emlxs_ub_priv_t		*ub_wait_head;	/* Unsolicited IO received */
1085 						/* before link up */
1086 	emlxs_ub_priv_t		*ub_wait_tail;	/* Unsolicited IO received */
1087 						/* before link up */
1088 
1089 #ifdef DHCHAP_SUPPORT
1090 	emlxs_port_dhc_t	port_dhc;
1091 #endif	/* DHCHAP_SUPPORT */
1092 
1093 #ifdef SFCT_SUPPORT
1094 	emlxs_memseg_t	*fct_memseg; /* Array */
1095 	uint32_t fct_memseg_cnt;
1096 
1097 /* Default buffer counts */
1098 #define	FCT_BUF_COUNT_2K		16
1099 #define	FCT_BUF_COUNT_4K		0
1100 #define	FCT_BUF_COUNT_8K		16
1101 #define	FCT_BUF_COUNT_16K		0
1102 #define	FCT_BUF_COUNT_32K		0
1103 #define	FCT_BUF_COUNT_64K		16
1104 #define	FCT_BUF_COUNT_128K		16
1105 #define	FCT_BUF_COUNT_256K		0
1106 
1107 	char			cfd_name[24];
1108 	stmf_port_provider_t	*port_provider;
1109 	fct_local_port_t	*fct_port;
1110 	uint8_t			fct_els_only_bmap;
1111 	uint32_t		fct_flags;
1112 
1113 #define	FCT_STATE_PORT_ONLINE		0x00000001
1114 #define	FCT_STATE_NOT_ACKED		0x00000002
1115 #define	FCT_STATE_LINK_UP		0x00000010
1116 #define	FCT_STATE_LINK_UP_ACKED		0x00000020
1117 #define	FCT_STATE_FLOGI_CMPL		0x00000040
1118 
1119 	emlxs_tgtport_stat_t	fct_stat;
1120 
1121 	/* Used to save fct_cmd for deferred unsol ELS commands, except FLOGI */
1122 	emlxs_buf_t		*fct_wait_head;
1123 	emlxs_buf_t		*fct_wait_tail;
1124 
1125 	/* Used to save context for deferred unsol FLOGIs */
1126 	fct_flogi_xchg_t	fx;
1127 
1128 #ifdef FCT_IO_TRACE
1129 	emlxs_iotrace_t		*iotrace;
1130 	uint16_t		iotrace_cnt;
1131 	uint16_t		iotrace_index;
1132 	kmutex_t		iotrace_mtx;
1133 #endif /* FCT_IO_TRACE */
1134 
1135 #endif /* SFCT_SUPPORT */
1136 
1137 	uint32_t		clean_address_timer;
1138 	emlxs_buf_t		*clean_address_sbp;
1139 
1140 #ifdef SAN_DIAG_SUPPORT
1141 	uint8_t			sd_io_latency_state;
1142 #define	SD_INVALID	0x00
1143 #define	SD_COLLECTING	0x01
1144 #define	SD_STOPPED	0x02
1145 
1146 	/* SD event management list */
1147 	uint32_t		sd_event_mask;   /* bit-mask */
1148 	emlxs_dfc_event_t	sd_events[MAX_DFC_EVENTS];
1149 #endif
1150 
1151 } emlxs_port_t;
1152 
1153 
1154 /* Host Attn reg */
1155 #define	FC_HA_REG(_hba)		((volatile uint32_t *) \
1156 				    ((_hba)->sli.sli3.ha_reg_addr))
1157 
1158 /* Chip Attn reg */
1159 #define	FC_CA_REG(_hba)		((volatile uint32_t *) \
1160 				    ((_hba)->sli.sli3.ca_reg_addr))
1161 
1162 /* Host Status reg */
1163 #define	FC_HS_REG(_hba)		((volatile uint32_t *) \
1164 				    ((_hba)->sli.sli3.hs_reg_addr))
1165 
1166 /* Host Cntl reg */
1167 #define	FC_HC_REG(_hba)		((volatile uint32_t *) \
1168 				    ((_hba)->sli.sli3.hc_reg_addr))
1169 
1170 /* BIU Configuration reg */
1171 #define	FC_BC_REG(_hba)		((volatile uint32_t *) \
1172 				    ((_hba)->sli.sli3.bc_reg_addr))
1173 
1174 /* Used by SBUS adapter */
1175 /* TITAN Cntl reg */
1176 #define	FC_SHC_REG(_hba)	((volatile uint32_t *) \
1177 				    ((_hba)->sli.sli3.shc_reg_addr))
1178 
1179 /* TITAN Status reg */
1180 #define	FC_SHS_REG(_hba)	((volatile uint32_t *) \
1181 				    ((_hba)->sli.sli3.shs_reg_addr))
1182 
1183 /* TITAN Update reg */
1184 #define	FC_SHU_REG(_hba)	((volatile uint32_t *) \
1185 				    ((_hba)->sli.sli3.shu_reg_addr))
1186 
1187 /* MPU Semaphore reg */
1188 #define	FC_SEMA_REG(_hba)	((volatile uint32_t *)\
1189 				    ((_hba)->sli.sli4.MPUEPSemaphore_reg_addr))
1190 
1191 /* Bootstrap Mailbox Doorbell reg */
1192 #define	FC_MBDB_REG(_hba)	((volatile uint32_t *) \
1193 				    ((_hba)->sli.sli4.MBDB_reg_addr))
1194 
1195 /* MQ Doorbell reg */
1196 #define	FC_MQDB_REG(_hba)	((volatile uint32_t *) \
1197 				    ((_hba)->sli.sli4.MQDB_reg_addr))
1198 
1199 /* CQ Doorbell reg */
1200 #define	FC_CQDB_REG(_hba)	((volatile uint32_t *) \
1201 				    ((_hba)->sli.sli4.CQDB_reg_addr))
1202 
1203 /* WQ Doorbell reg */
1204 #define	FC_WQDB_REG(_hba)	((volatile uint32_t *) \
1205 				    ((_hba)->sli.sli4.WQDB_reg_addr))
1206 
1207 /* RQ Doorbell reg */
1208 #define	FC_RQDB_REG(_hba)	((volatile uint32_t *) \
1209 				    ((_hba)->sli.sli4.RQDB_reg_addr))
1210 
1211 
1212 #define	FC_SLIM2_MAILBOX(_hba)	((MAILBOX *)(_hba)->sli.sli3.slim2.virt)
1213 
1214 #define	FC_SLIM1_MAILBOX(_hba)	((MAILBOX *)(_hba)->sli.sli3.slim_addr)
1215 
1216 #define	FC_MAILBOX(_hba)	(((_hba)->flag & FC_SLIM2_MODE) ? \
1217 	FC_SLIM2_MAILBOX(_hba) : FC_SLIM1_MAILBOX(_hba))
1218 
1219 #define	WRITE_CSR_REG(_hba, _regp, _value) ddi_put32(\
1220 	(_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp), \
1221 	(uint32_t)(_value))
1222 
1223 #define	READ_CSR_REG(_hba, _regp) ddi_get32(\
1224 	(_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp))
1225 
1226 #define	WRITE_SLIM_ADDR(_hba, _regp, _value) ddi_put32(\
1227 	(_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp), \
1228 	(uint32_t)(_value))
1229 
1230 #define	READ_SLIM_ADDR(_hba, _regp) ddi_get32(\
1231 	(_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp))
1232 
1233 #define	WRITE_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_put32(\
1234 	(_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1235 	(uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1236 
1237 #define	READ_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_get32(\
1238 	(_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1239 	(uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1240 
1241 /* Used by SBUS adapter */
1242 #define	WRITE_SBUS_CSR_REG(_hba, _regp, _value)	ddi_put32(\
1243 	(_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp), \
1244 	(uint32_t)(_value))
1245 
1246 #define	READ_SBUS_CSR_REG(_hba, _regp) ddi_get32(\
1247 	(_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp))
1248 
1249 #define	SBUS_WRITE_FLASH_COPY(_hba, _offset, _value) ddi_put8(\
1250 	(_hba)->sli.sli3.sbus_flash_acc_handle, \
1251 	(uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1252 	(_offset)), (uint8_t)(_value))
1253 
1254 #define	SBUS_READ_FLASH_COPY(_hba, _offset) ddi_get8(\
1255 	(_hba)->sli.sli3.sbus_flash_acc_handle, \
1256 	(uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1257 	(_offset)))
1258 
1259 /* SLI4 registers */
1260 #define	WRITE_BAR0_REG(_hba, _regp, _value) ddi_put32(\
1261 	(_hba)->sli.sli4.bar0_acc_handle, (uint32_t *)(_regp), \
1262 	(uint32_t)(_value))
1263 
1264 #define	READ_BAR0_REG(_hba, _regp) ddi_get32(\
1265 	(_hba)->sli.sli4.bar0_acc_handle, (uint32_t *)(_regp))
1266 
1267 #define	WRITE_BAR1_REG(_hba, _regp, _value) ddi_put32(\
1268 	(_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp), \
1269 	(uint32_t)(_value))
1270 
1271 #define	READ_BAR1_REG(_hba, _regp) ddi_get32(\
1272 	(_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp))
1273 
1274 #define	WRITE_BAR2_REG(_hba, _regp, _value) ddi_put32(\
1275 	(_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp), \
1276 	(uint32_t)(_value))
1277 
1278 #define	READ_BAR2_REG(_hba, _regp) ddi_get32(\
1279 	(_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp))
1280 
1281 
1282 #define	EMLXS_STATE_CHANGE(_hba, _state)\
1283 {									\
1284 	mutex_enter(&EMLXS_PORT_LOCK);					\
1285 	EMLXS_STATE_CHANGE_LOCKED((_hba), (_state));			\
1286 	mutex_exit(&EMLXS_PORT_LOCK);					\
1287 }
1288 
1289 /* Used when EMLXS_PORT_LOCK is already held */
1290 #define	EMLXS_STATE_CHANGE_LOCKED(_hba, _state)			\
1291 {									\
1292 	if ((_hba)->state != (_state))					\
1293 	{								\
1294 		uint32_t _st = _state;					\
1295 		EMLXS_MSGF(EMLXS_CONTEXT,				\
1296 			&emlxs_state_msg, "%s --> %s",			\
1297 			emlxs_ffstate_xlate((_hba)->state),		\
1298 			emlxs_ffstate_xlate(_state));			\
1299 			(_hba)->state = (_state);			\
1300 		if ((_st) == FC_ERROR)					\
1301 		{							\
1302 			(_hba)->flag |= FC_HARDWARE_ERROR;		\
1303 		}							\
1304 	}								\
1305 }
1306 
1307 #ifdef FMA_SUPPORT
1308 #define	EMLXS_CHK_ACC_HANDLE(_hba, _acc) \
1309 	if (emlxs_fm_check_acc_handle(_hba, _acc) != DDI_FM_OK) { \
1310 		EMLXS_MSGF(EMLXS_CONTEXT, \
1311 		    &emlxs_invalid_access_handle_msg, NULL); \
1312 	}
1313 #endif  /* FMA_SUPPORT */
1314 
1315 /*
1316  * This is the HBA control area for the adapter
1317  */
1318 
1319 #ifdef MODSYM_SUPPORT
1320 
1321 typedef struct emlxs_modsym
1322 {
1323 	ddi_modhandle_t  mod_fctl;	/* For Leadville */
1324 
1325 	/* Leadville (fctl) */
1326 	int		(*fc_fca_attach)(dev_info_t *, fc_fca_tran_t *);
1327 	int		(*fc_fca_detach)(dev_info_t *);
1328 	int		(*fc_fca_init)(struct dev_ops *);
1329 
1330 #ifdef SFCT_SUPPORT
1331 	uint32_t	fct_modopen;
1332 	uint32_t	reserved;  /* Padding for alignment */
1333 
1334 	ddi_modhandle_t  mod_fct;	/* For Comstar */
1335 	ddi_modhandle_t  mod_stmf;	/* For Comstar */
1336 
1337 	/* Comstar (fct) */
1338 	void*	(*fct_alloc)(fct_struct_id_t, int, int);
1339 	void	(*fct_free)(void *);
1340 	void*	(*fct_scsi_task_alloc)(void *, uint16_t, uint32_t, uint8_t *,
1341 			uint16_t, uint16_t);
1342 	int	(*fct_register_local_port)(fct_local_port_t *);
1343 	void	(*fct_deregister_local_port)(fct_local_port_t *);
1344 	void	(*fct_handle_event)(fct_local_port_t *, int, uint32_t, caddr_t);
1345 	void	(*fct_post_rcvd_cmd)(fct_cmd_t *, stmf_data_buf_t *);
1346 	void	(*fct_ctl)(void *, int, void *);
1347 	void	(*fct_queue_cmd_for_termination)(fct_cmd_t *, fct_status_t);
1348 	void	(*fct_send_response_done)(fct_cmd_t *, fct_status_t, uint32_t);
1349 	void	(*fct_send_cmd_done)(fct_cmd_t *, fct_status_t, uint32_t);
1350 	void	(*fct_scsi_data_xfer_done)(fct_cmd_t *, stmf_data_buf_t *,
1351 			uint32_t);
1352 	fct_status_t	(*fct_port_shutdown)
1353 				(fct_local_port_t *, uint32_t, char *);
1354 	fct_status_t	(*fct_port_initialize)
1355 				(fct_local_port_t *, uint32_t, char *);
1356 	void		(*fct_cmd_fca_aborted)
1357 				(fct_cmd_t *, fct_status_t, int);
1358 	fct_status_t	(*fct_handle_rcvd_flogi)
1359 				(fct_local_port_t *, fct_flogi_xchg_t *);
1360 
1361 	/* Comstar (stmf) */
1362 	void*  (*stmf_alloc)(stmf_struct_id_t, int, int);
1363 	void   (*stmf_free)(void *);
1364 	void	(*stmf_deregister_port_provider) (stmf_port_provider_t *);
1365 	int	(*stmf_register_port_provider) (stmf_port_provider_t *);
1366 #endif /* SFCT_SUPPORT */
1367 } emlxs_modsym_t;
1368 extern emlxs_modsym_t emlxs_modsym;
1369 
1370 #define	MODSYM(_f)	emlxs_modsym._f
1371 
1372 #else
1373 
1374 #define	MODSYM(_f)	_f
1375 
1376 #endif /* MODSYM_SUPPORT */
1377 
1378 
1379 
1380 typedef struct RPIHdrTmplate
1381 {
1382 	uint32_t	Word[16];  /* 64 bytes */
1383 } RPIHdrTmplate_t;
1384 
1385 
1386 typedef struct EQ_DESC
1387 {
1388 	uint16_t	host_index;
1389 	uint16_t	max_index;
1390 	uint16_t	qid;
1391 	uint16_t	msix_vector;
1392 	kmutex_t	lastwq_lock;
1393 	uint16_t	lastwq;
1394 	MBUF_INFO	addr;
1395 
1396 	/* Statistics */
1397 	uint32_t	max_proc;
1398 	uint32_t	isr_count;
1399 	uint32_t	num_proc;
1400 } EQ_DESC_t;
1401 
1402 
1403 typedef struct CQ_DESC
1404 {
1405 	uint16_t	host_index;
1406 	uint16_t	max_index;
1407 	uint16_t	qid;
1408 	uint16_t	eqid;
1409 	uint16_t	type;
1410 #define	EMLXS_CQ_TYPE_GROUP1	1  /* associated with a MQ and async events */
1411 #define	EMLXS_CQ_TYPE_GROUP2	2  /* associated with a WQ and RQ */
1412 	uint16_t	rsvd;
1413 
1414 	MBUF_INFO	addr;
1415 	CHANNEL		*channelp; /* ptr to CHANNEL associated with CQ */
1416 
1417 	/* Statistics */
1418 	uint32_t	max_proc;
1419 	uint32_t	isr_count;
1420 	uint32_t	num_proc;
1421 } CQ_DESC_t;
1422 
1423 
1424 typedef struct WQ_DESC
1425 {
1426 	uint16_t	host_index;
1427 	uint16_t	max_index;
1428 	uint16_t	port_index;
1429 	uint16_t	release_depth;
1430 #define	WQE_RELEASE_DEPTH	(8 * EMLXS_NUM_WQ_PAGES)
1431 	uint16_t	qid;
1432 	uint16_t	cqid;
1433 	MBUF_INFO	addr;
1434 
1435 	/* Statistics */
1436 	uint32_t	num_proc;
1437 	uint32_t	num_busy;
1438 } WQ_DESC_t;
1439 
1440 
1441 typedef struct RQ_DESC
1442 {
1443 	uint16_t	host_index;
1444 	uint16_t	max_index;
1445 	uint16_t	qid;
1446 	uint16_t	cqid;
1447 
1448 	MBUF_INFO	addr;
1449 	MBUF_INFO	rqb[RQ_DEPTH];
1450 
1451 	kmutex_t	lock;
1452 
1453 	/* Statistics */
1454 	uint32_t	num_proc;
1455 } RQ_DESC_t;
1456 
1457 
1458 typedef struct RXQ_DESC
1459 {
1460 	kmutex_t	lock;
1461 	emlxs_queue_t	active;
1462 
1463 } RXQ_DESC_t;
1464 
1465 
1466 typedef struct MQ_DESC
1467 {
1468 	uint16_t	host_index;
1469 	uint16_t	max_index;
1470 	uint16_t	qid;
1471 	uint16_t	cqid;
1472 	MBUF_INFO	addr;
1473 } MQ_DESC_t;
1474 
1475 
1476 /* Define the number of queues the driver will be using */
1477 #define	EMLXS_MAX_EQS	EMLXS_MSI_MAX_INTRS
1478 #define	EMLXS_MAX_WQS	EMLXS_MAX_WQS_PER_EQ * EMLXS_MAX_EQS
1479 #define	EMLXS_MAX_RQS	2	/* ONLY 1 pair is allowed */
1480 #define	EMLXS_MAX_MQS	1
1481 
1482 /* One CQ for each WQ & (RQ pair) plus one for the MQ */
1483 #define	EMLXS_MAX_CQS	(EMLXS_MAX_WQS + (EMLXS_MAX_RQS/2) + 1)
1484 
1485 /* The First CQ created is ALWAYS for mbox / event handling */
1486 #define	EMLXS_CQ_MBOX		0
1487 
1488 /* The Second CQ created is ALWAYS for unsol rcv handling */
1489 /* At this time we are allowing ONLY 1 pair of RQs */
1490 #define	EMLXS_CQ_RCV		1
1491 
1492 /* The remaining CQs are for WQ completions */
1493 #define	EMLXS_CQ_OFFSET_WQ	2
1494 
1495 
1496 /* FCFI RQ Configuration */
1497 #define	EMLXS_FCFI_RQ0_INDEX	0
1498 #define	EMLXS_FCFI_RQ0_RMASK	0 /* match all */
1499 #define	EMLXS_FCFI_RQ0_RCTL	0 /* match all */
1500 #define	EMLXS_FCFI_RQ0_TMASK	0 /* match all */
1501 #define	EMLXS_FCFI_RQ0_TYPE	0 /* match all */
1502 
1503 #define	EMLXS_RXQ_ELS		0
1504 #define	EMLXS_RXQ_CT		1
1505 #define	EMLXS_MAX_RXQS		2
1506 
1507 #define	PCI_CONFIG_SIZE   0x80
1508 
1509 typedef struct emlxs_sli3
1510 {
1511 	/* SLIM management */
1512 	MATCHMAP	slim2;
1513 
1514 	/* HBQ management */
1515 	uint32_t	hbq_count;	/* Total number of HBQs */
1516 					/* configured */
1517 	HBQ_INIT_t	hbq_table[EMLXS_NUM_HBQ];
1518 
1519 	/* Adapter memory management */
1520 	caddr_t		csr_addr;
1521 	caddr_t		slim_addr;
1522 	ddi_acc_handle_t csr_acc_handle;
1523 	ddi_acc_handle_t slim_acc_handle;
1524 
1525 	/* SBUS adapter management */
1526 	caddr_t		sbus_flash_addr;	/* Virt addr of R/W */
1527 						/* Flash */
1528 	caddr_t		sbus_core_addr;		/* Virt addr of TITAN */
1529 						/* CORE */
1530 	caddr_t		sbus_csr_addr;		/* Virt addr of TITAN */
1531 						/* CSR */
1532 	ddi_acc_handle_t sbus_flash_acc_handle;
1533 	ddi_acc_handle_t sbus_core_acc_handle;
1534 	ddi_acc_handle_t sbus_csr_handle;
1535 
1536 	/* SLI 2/3 Adapter register management */
1537 	uint32_t	*bc_reg_addr;	/* virtual offset for BIU */
1538 					/* config reg */
1539 	uint32_t	*ha_reg_addr;	/* virtual offset for host */
1540 					/* attn reg */
1541 	uint32_t	*hc_reg_addr;	/* virtual offset for host */
1542 					/* ctl reg */
1543 	uint32_t	*ca_reg_addr;	/* virtual offset for FF */
1544 					/* attn reg */
1545 	uint32_t	*hs_reg_addr;	/* virtual offset for */
1546 					/* status reg */
1547 	uint32_t	*shc_reg_addr;	/* virtual offset for SBUS */
1548 					/* Ctrl reg */
1549 	uint32_t	*shs_reg_addr;	/* virtual offset for SBUS */
1550 					/* Status reg */
1551 	uint32_t	*shu_reg_addr;	/* virtual offset for SBUS */
1552 					/* Update reg */
1553 	uint16_t	hgp_ring_offset;
1554 	uint16_t	hgp_hbq_offset;
1555 	uint16_t	iocb_cmd_size;
1556 	uint16_t	iocb_rsp_size;
1557 	uint32_t	hc_copy;	/* local copy of HC register */
1558 
1559 	/* Ring management */
1560 	uint32_t	ring_count;
1561 	emlxs_ring_t	ring[MAX_RINGS];
1562 	kmutex_t	ring_cmd_lock[MAX_RINGS];
1563 	uint8_t		ring_masks[4];	/* number of masks/rings used */
1564 	uint8_t		ring_rval[6];
1565 	uint8_t		ring_rmask[6];
1566 	uint8_t		ring_tval[6];
1567 	uint8_t		ring_tmask[6];
1568 
1569 	/* Protected by EMLXS_FCTAB_LOCK */
1570 	MATCHMAP	**bpl_table; /* iotag table for */
1571 					/* bpl buffers */
1572 	uint32_t	mem_bpl_size;
1573 } emlxs_sli3_t;
1574 
1575 typedef struct emlxs_sli4
1576 {
1577 	MATCHMAP	bootstrapmb;
1578 	caddr_t		bar0_addr;
1579 	caddr_t		bar1_addr;
1580 	caddr_t		bar2_addr;
1581 	ddi_acc_handle_t bar0_acc_handle;
1582 	ddi_acc_handle_t bar1_acc_handle;
1583 	ddi_acc_handle_t bar2_acc_handle;
1584 
1585 	/* SLI4 Adapter register management */
1586 	uint32_t	*MPUEPSemaphore_reg_addr;
1587 	uint32_t	*MBDB_reg_addr;
1588 
1589 	uint32_t	*CQDB_reg_addr;
1590 	uint32_t	*MQDB_reg_addr;
1591 	uint32_t	*WQDB_reg_addr;
1592 	uint32_t	*RQDB_reg_addr;
1593 	uint32_t	*SEMA_reg_addr;
1594 	uint32_t	*STATUS_reg_addr;
1595 	uint32_t	*CNTL_reg_addr;
1596 	uint32_t	*ERR1_reg_addr;
1597 	uint32_t	*ERR2_reg_addr;
1598 	uint32_t	*PHYSDEV_reg_addr;
1599 
1600 	uint32_t	flag;
1601 #define	EMLXS_SLI4_INTR_ENABLED		0x00000001
1602 #define	EMLXS_SLI4_HW_ERROR		0x00000002
1603 #define	EMLXS_SLI4_DOWN_LINK		0x00000004
1604 #define	EMLXS_SLI4_PHON			0x00000008
1605 #define	EMLXS_SLI4_PHWQ			0x00000010
1606 #define	EMLXS_SLI4_NULL_XRI		0x00000020
1607 
1608 #define	EMLXS_SLI4_FCF_INIT		0x10000000
1609 #define	EMLXS_SLI4_FCOE_MODE		0x80000000
1610 
1611 #define	SLI4_FCOE_MODE	(hba->sli.sli4.flag & EMLXS_SLI4_FCOE_MODE)
1612 #define	SLI4_FC_MODE	(!SLI4_FCOE_MODE)
1613 
1614 
1615 
1616 	uint16_t	XRICount;
1617 	uint16_t	XRIExtCount;
1618 	uint16_t	XRIExtSize;
1619 	uint16_t	XRIBase[MAX_EXTENTS];
1620 
1621 	uint16_t	RPICount;
1622 	uint16_t	RPIExtCount;
1623 	uint16_t	RPIExtSize;
1624 	uint16_t	RPIBase[MAX_EXTENTS];
1625 
1626 	uint16_t	VPICount;
1627 	uint16_t	VPIExtCount;
1628 	uint16_t	VPIExtSize;
1629 	uint16_t	VPIBase[MAX_EXTENTS];
1630 
1631 	uint16_t	VFICount;
1632 	uint16_t	VFIExtCount;
1633 	uint16_t	VFIExtSize;
1634 	uint16_t	VFIBase[MAX_EXTENTS];
1635 
1636 	uint16_t	FCFICount;
1637 
1638 	kmutex_t	fcf_lock;
1639 	FCFTable_t	fcftab;
1640 	VFIobj_t	*VFI_table;
1641 
1642 	/* Save Config Region 23 info */
1643 	tlv_fcoe_t	cfgFCOE;
1644 	tlv_fcfconnectlist_t	cfgFCF;
1645 
1646 	MBUF_INFO	slim2;
1647 	MBUF_INFO	dump_region;
1648 #define	EMLXS_DUMP_REGION_SIZE	1024
1649 
1650 	RPIobj_t	*RPIp;
1651 	MBUF_INFO	HeaderTmplate;
1652 	XRIobj_t	*XRIp;
1653 
1654 	/* Double linked list for available XRIs */
1655 	XRIobj_t	*XRIfree_f;
1656 	XRIobj_t	*XRIfree_b;
1657 	uint32_t	xrif_count;
1658 	uint32_t	mem_sgl_size;
1659 
1660 	/* Double linked list for XRIs in use */
1661 	XRIobj_t	*XRIinuse_f;
1662 	XRIobj_t	*XRIinuse_b;
1663 	uint32_t	xria_count;
1664 
1665 	kmutex_t	que_lock[EMLXS_MAX_WQS];
1666 	EQ_DESC_t	eq[EMLXS_MAX_EQS];
1667 	CQ_DESC_t	cq[EMLXS_MAX_CQS];
1668 	WQ_DESC_t	wq[EMLXS_MAX_WQS];
1669 	RQ_DESC_t	rq[EMLXS_MAX_RQS];
1670 	RXQ_DESC_t	rxq[EMLXS_MAX_RXQS];
1671 	MQ_DESC_t	mq;
1672 	uint32_t	que_stat_timer;
1673 
1674 	uint32_t	ue_mask_lo;
1675 	uint32_t	ue_mask_hi;
1676 
1677 	sli_params_t	param;
1678 
1679 	uint8_t port_name[4];
1680 	uint32_t link_number;
1681 
1682 } emlxs_sli4_t;
1683 
1684 
1685 typedef struct emlxs_sli_api
1686 {
1687 	int		(*sli_map_hdw)();
1688 	void		(*sli_unmap_hdw)();
1689 	int32_t		(*sli_online)();
1690 	void		(*sli_offline)();
1691 	uint32_t	(*sli_hba_reset)();
1692 	void		(*sli_hba_kill)();
1693 	void		(*sli_issue_iocb_cmd)();
1694 	uint32_t	(*sli_issue_mbox_cmd)();
1695 	uint32_t	(*sli_prep_fct_iocb)();
1696 	uint32_t	(*sli_prep_fcp_iocb)();
1697 	uint32_t	(*sli_prep_ip_iocb)();
1698 	uint32_t	(*sli_prep_els_iocb)();
1699 	uint32_t	(*sli_prep_ct_iocb)();
1700 	void		(*sli_poll_intr)();
1701 	int32_t		(*sli_intx_intr)();
1702 	uint32_t	(*sli_msi_intr)();
1703 	void		(*sli_disable_intr)();
1704 	void		(*sli_timer)();
1705 	void		(*sli_poll_erratt)();
1706 	uint32_t	(*sli_reg_did)();
1707 	uint32_t	(*sli_unreg_node)();
1708 
1709 } emlxs_sli_api_t;
1710 
1711 
1712 typedef struct emlxs_hba
1713 {
1714 	dev_info_t	*dip;
1715 	int32_t		emlxinst;
1716 	int32_t		ddiinst;
1717 	uint8_t		pci_function_number;
1718 	uint8_t		pci_device_number;
1719 	uint8_t		pci_bus_number;
1720 	uint8_t		pci_cap_offset[PCI_CAP_MAX_PTR];
1721 	uint16_t	pci_ecap_offset[PCI_EXT_CAP_MAX_PTR];
1722 
1723 #ifdef FMA_SUPPORT
1724 	int32_t		fm_caps;	/* FMA capabilities */
1725 #endif	/* FMA_SUPPORT */
1726 	fc_fca_tran_t	*fca_tran;
1727 
1728 	/* DMA attributes */
1729 	ddi_dma_attr_t	dma_attr;
1730 	ddi_dma_attr_t	dma_attr_ro;
1731 	ddi_dma_attr_t	dma_attr_1sg;
1732 	ddi_dma_attr_t	dma_attr_fcip_rsp;
1733 
1734 	/* HBA Info */
1735 	emlxs_model_t	model_info;
1736 	emlxs_vpd_t	vpd;	/* vital product data */
1737 	NAME_TYPE	wwnn;
1738 	NAME_TYPE	wwpn;
1739 	char		snn[256];
1740 	char		spn[256];
1741 	PROG_ID		load_list[MAX_LOAD_ENTRY];
1742 	WAKE_UP_PARMS	wakeup_parms;
1743 	uint32_t	max_nodes;
1744 	uint32_t	io_throttle;
1745 	uint32_t	io_active;
1746 	uint32_t	bus_type;
1747 #define	PCI_FC  	0
1748 #define	SBUS_FC		1
1749 	uint32_t	sli_intf;
1750 #define	SLI_INTF_VALID_MASK		0xe0000000
1751 #define	SLI_INTF_VALID			0xc0000000
1752 
1753 #define	SLI_INTF_HINT2_MASK		0x1f000000
1754 #define	SLI_INTF_HINT2_0		0x00000000
1755 
1756 #define	SLI_INTF_HINT1_MASK		0x00ff0000
1757 #define	SLI_INTF_HINT1_0		0x00000000
1758 #define	SLI_INTF_HINT1_1		0x00010000
1759 #define	SLI_INTF_HINT1_2		0x00020000
1760 
1761 #define	SLI_INTF_IF_TYPE_MASK		0x0000f000
1762 #define	SLI_INTF_IF_TYPE_0		0x00000000
1763 #define	SLI_INTF_IF_TYPE_1		0x00001000
1764 #define	SLI_INTF_IF_TYPE_2		0x00002000
1765 #define	SLI_INTF_IF_TYPE_3		0x00003000
1766 
1767 #define	SLI_INTF_FAMILY_MASK		0x00000f00
1768 #define	SLI_INTF_FAMILY_BE2		0x00000000
1769 #define	SLI_INTF_FAMILY_BE3		0x00000100
1770 #define	SLI_INTF_FAMILY_LANCER_A	0x00000a00
1771 #define	SLI_INTF_FAMILY_LANCER_B	0x00000b00
1772 
1773 #define	SLI_INTF_SLI_REV_MASK		0x000000f0
1774 #define	SLI_INTF_SLI_REV_NONE		0x00000000
1775 #define	SLI_INTF_SLI_REV_3		0x00000030
1776 #define	SLI_INTF_SLI_REV_4		0x00000040
1777 
1778 #define	SLI_INTF_RESERVED1		0x0000000e
1779 
1780 #define	SLI_INTF_FUNC_TYPE_MASK		0x00000001
1781 #define	SLI_INTF_FUNC_PF		0x00000000
1782 #define	SLI_INTF_FUNC_VF		0x00000001
1783 
1784 	/* Link management */
1785 	uint32_t	link_event_tag;
1786 	uint8_t		topology;
1787 	uint8_t		linkspeed;
1788 	uint16_t	qos_linkspeed;
1789 	uint32_t	linkup_wait_flag;
1790 	kcondvar_t	linkup_lock_cv;
1791 	kmutex_t	linkup_lock;
1792 
1793 	/* Memory Pool management */
1794 	emlxs_memseg_t	memseg[FC_MAX_SEG];	/* memory for buffer */
1795 							/* structures */
1796 	kmutex_t	memget_lock;	/* locks all memory pools get */
1797 	kmutex_t	memput_lock;	/* locks all memory pools put */
1798 	uint32_t	mem_timer;
1799 
1800 	/* Fibre Channel Service Parameters */
1801 	SERV_PARM	sparam;
1802 	uint32_t	fc_edtov;	/* E_D_TOV timer value */
1803 	uint32_t	fc_arbtov;	/* ARB_TOV timer value */
1804 	uint32_t	fc_ratov;	/* R_A_TOV timer value */
1805 	uint32_t	fc_rttov;	/* R_T_TOV timer value */
1806 	uint32_t	fc_altov;	/* AL_TOV timer value */
1807 	uint32_t	fc_crtov;	/* C_R_TOV timer value */
1808 	uint32_t	fc_citov;	/* C_I_TOV timer value */
1809 
1810 	/* Adapter State management */
1811 	int32_t		state;
1812 #define	FC_ERROR		0x01	/* Adapter shutdown */
1813 #define	FC_KILLED		0x02	/* Adapter interlocked/killed */
1814 #define	FC_WARM_START		0x03	/* Adapter reset, but not restarted */
1815 #define	FC_INIT_START		0x10	/* Adapter restarted */
1816 #define	FC_INIT_NVPARAMS	0x11
1817 #define	FC_INIT_REV		0x12
1818 #define	FC_INIT_CFGPORT		0x13
1819 #define	FC_INIT_CFGRING		0x14
1820 #define	FC_INIT_INITLINK	0x15
1821 #define	FC_LINK_DOWN		0x20
1822 #define	FC_LINK_DOWN_PERSIST	0x21
1823 #define	FC_LINK_UP		0x30
1824 #define	FC_CLEAR_LA		0x31
1825 #define	FC_READY		0x40
1826 
1827 	uint32_t	flag;
1828 #define	FC_ONLINING_MODE	0x00000001
1829 #define	FC_ONLINE_MODE		0x00000002
1830 #define	FC_OFFLINING_MODE	0x00000004
1831 #define	FC_OFFLINE_MODE		0x00000008
1832 
1833 #define	FC_NPIV_ENABLED		0x00000010	/* NPIV enabled on adapter    */
1834 #define	FC_NPIV_SUPPORTED	0x00000020	/* NPIV supported on fabric   */
1835 #define	FC_NPIV_UNSUPPORTED	0x00000040	/* NPIV unsupported on fabric */
1836 #define	FC_NPIV_LINKUP		0x00000100	/* NPIV enabled, supported, */
1837 						/* and link is ready */
1838 #define	FC_NPIV_DELAY_REQUIRED	0x00000200	/* Delay issuing FLOGI/FDISC */
1839 						/* and NameServer cmds */
1840 
1841 #define	FC_BOOTSTRAPMB_INIT	0x00000400
1842 #define	FC_FIP_SUPPORTED	0x00000800	/* FIP supported */
1843 
1844 #define	FC_FABRIC_ATTACHED	0x00001000
1845 #define	FC_PT_TO_PT		0x00002000
1846 #define	FC_BYPASSED_MODE	0x00004000
1847 #define	FC_MENLO_MODE		0x00008000	/* Menlo maintenance mode */
1848 
1849 #define	FC_DUMP_SAFE		0x00010000	/* Safe to DUMP */
1850 #define	FC_DUMP_ACTIVE		0x00020000	/* DUMP in progress */
1851 #define	FC_NEW_FABRIC		0x00040000
1852 
1853 #define	FC_SLIM2_MODE		0x00100000	/* SLIM in host memory */
1854 #define	FC_INTERLOCKED		0x00200000
1855 #define	FC_HBQ_ENABLED		0x00400000
1856 #define	FC_ASYNC_EVENTS		0x00800000
1857 
1858 #define	FC_ILB_MODE		0x01000000
1859 #define	FC_ELB_MODE		0x02000000
1860 #define	FC_LOOPBACK_MODE	0x03000000	/* Loopback Mode Mask */
1861 #define	FC_DUMP			0x04000000	/* DUMP in progress */
1862 #define	FC_SHUTDOWN		0x08000000	/* SHUTDOWN in progress */
1863 
1864 #define	FC_OVERTEMP_EVENT	0x10000000	/* FC_ERROR reason: */
1865 						/* over temperature event */
1866 #define	FC_MBOX_TIMEOUT		0x20000000	/* FC_ERROR reason: */
1867 						/* mailbox timeout event */
1868 #define	FC_DMA_CHECK_ERROR	0x40000000	/* Shared memory (slim,..) */
1869 						/* DMA handle went bad */
1870 #define	FC_HARDWARE_ERROR	0x80000000	/* FC_ERROR state triggered */
1871 
1872 #define	FC_RESET_MASK		0x00030C1F	/* Bits to protect during */
1873 						/* a hard reset */
1874 #define	FC_LINKDOWN_MASK	0xFFF30C1F	/* Bits to protect during */
1875 						/* a linkdown */
1876 
1877 	uint32_t fw_timer;
1878 	uint32_t fw_flag;
1879 #define	FW_UPDATE_NEEDED	0x00000001
1880 #define	FW_UPDATE_KERNEL	0x00000002
1881 
1882 	uint32_t temperature;			/* Last reported temperature */
1883 
1884 	/* SBUS adapter management */
1885 	caddr_t		sbus_pci_addr;		/* Virt addr of TITAN */
1886 						/* pci config */
1887 	ddi_acc_handle_t sbus_pci_handle;
1888 
1889 	/* PCI BUS adapter management */
1890 	caddr_t		pci_addr;
1891 	ddi_acc_handle_t pci_acc_handle;
1892 
1893 	uint32_t	sli_mode;
1894 #define	EMLXS_HBA_SLI1_MODE	1
1895 #define	EMLXS_HBA_SLI2_MODE	2
1896 #define	EMLXS_HBA_SLI3_MODE	3
1897 #define	EMLXS_HBA_SLI4_MODE	4
1898 
1899 	/* SLI private data */
1900 	union {
1901 		emlxs_sli3_t sli3;
1902 		emlxs_sli4_t sli4;
1903 	} sli;
1904 
1905 	/* SLI API entry point routines */
1906 	emlxs_sli_api_t sli_api;
1907 
1908 	uint32_t	io_poll_count;	/* Number of poll commands */
1909 					/* in progress */
1910 
1911 	/* IO Completion management */
1912 	uint32_t	iodone_count;	/* Number of IO's on done Q */
1913 	/* Protected by EMLXS_PORT_LOCK  */
1914 	emlxs_buf_t	*iodone_list;	/* fc_packet being deferred */
1915 	emlxs_buf_t	*iodone_tail;	/* fc_packet being deferred */
1916 	emlxs_thread_t	iodone_thread;
1917 	emlxs_thread_t	*spawn_thread_head;
1918 	emlxs_thread_t	*spawn_thread_tail;
1919 	kmutex_t	spawn_lock;
1920 	uint32_t	spawn_open;
1921 
1922 	/* IO Channel management */
1923 	int32_t		chan_count;
1924 	emlxs_channel_t	chan[MAX_CHANNEL];
1925 	kmutex_t	channel_tx_lock;
1926 	uint8_t		channel_fcp;	/* Default channel to use for FCP IO */
1927 #define	CHANNEL_FCT channel_fcp
1928 	uint8_t		channel_ip;	/* Default channel to use for IP IO */
1929 	uint8_t		channel_els;	/* Default channel to use for ELS IO */
1930 	uint8_t		channel_ct;	/* Default channel to use for CT IO */
1931 
1932 	/* IOTag management */
1933 	emlxs_buf_t	**fc_table;	/* sc_buf pointers indexed by */
1934 					/* iotag */
1935 	uint16_t	fc_iotag;	/* used to identify I/Os */
1936 	uint16_t	fc_oor_iotag;	/* OutOfRange (fc_table) iotags */
1937 					/* typically used for Abort/close */
1938 #define	EMLXS_MAX_ABORT_TAG	0x7fff
1939 	uint16_t	max_iotag;	/* ALL IOCBs except aborts */
1940 	kmutex_t	iotag_lock;
1941 	uint32_t	io_count;		/* No of IO holding */
1942 						/* regular iotag */
1943 	uint32_t	channel_tx_count;	/* No of IO on tx Q */
1944 
1945 	/* Mailbox Management */
1946 	uint32_t	mbox_queue_flag;
1947 	emlxs_queue_t	mbox_queue;
1948 	void		*mbox_mqe;	/* active mbox mqe */
1949 	void		*mbox_mbq;	/* active MAILBOXQ */
1950 	kcondvar_t	mbox_lock_cv;	/* MBX_SLEEP */
1951 	kmutex_t	mbox_lock;	/* MBX_SLEEP */
1952 	uint32_t	mbox_timer;
1953 
1954 	/* Interrupt management */
1955 	void		*intr_arg;
1956 	uint32_t	intr_unclaimed;
1957 	uint32_t	intr_autoClear;
1958 	uint32_t	intr_busy_cnt;
1959 
1960 	uint32_t	intr_flags;
1961 #define	EMLXS_INTX_INITED	0x0001
1962 #define	EMLXS_INTX_ADDED	0x0002
1963 #define	EMLXS_MSI_ENABLED	0x0010
1964 #define	EMLXS_MSI_INITED	0x0020
1965 #define	EMLXS_MSI_ADDED		0x0040
1966 #define	EMLXS_INTR_INITED	(EMLXS_INTX_INITED|EMLXS_MSI_INITED)
1967 #define	EMLXS_INTR_ADDED	(EMLXS_INTX_ADDED|EMLXS_MSI_ADDED)
1968 
1969 #ifdef MSI_SUPPORT
1970 	ddi_intr_handle_t *intr_htable;
1971 	uint32_t	*intr_pri;
1972 	int32_t		*intr_cap;
1973 	uint32_t	intr_count;
1974 	uint32_t	intr_type;
1975 	uint32_t	intr_cond;
1976 	uint32_t	intr_map[EMLXS_MSI_MAX_INTRS];
1977 	uint32_t	intr_mask;
1978 
1979 	kmutex_t	msiid_lock; /* for last_msiid */
1980 	int		last_msiid;
1981 
1982 	kmutex_t	intr_lock[EMLXS_MSI_MAX_INTRS];
1983 	int			chan2msi[MAX_CHANNEL];
1984 					/* Index is the channel id */
1985 	int			msi2chan[EMLXS_MSI_MAX_INTRS];
1986 					/* Index is the MSX-X msg id */
1987 #endif	/* MSI_SUPPORT */
1988 
1989 	uint32_t	heartbeat_timer;
1990 	uint32_t	heartbeat_flag;
1991 	uint32_t	heartbeat_active;
1992 
1993 	/* IOCTL management */
1994 	kmutex_t	ioctl_lock;
1995 	uint32_t	ioctl_flags;
1996 #define	EMLXS_OPEN		0x00000001
1997 #define	EMLXS_OPEN_EXCLUSIVE	0x00000002
1998 
1999 	/* Timer management */
2000 	kcondvar_t	timer_lock_cv;
2001 	kmutex_t	timer_lock;
2002 	timeout_id_t	timer_id;
2003 	uint32_t	timer_tics;
2004 	uint32_t	timer_flags;
2005 #define	EMLXS_TIMER_STARTED	0x0000001
2006 #define	EMLXS_TIMER_BUSY	0x0000002
2007 #define	EMLXS_TIMER_KILL	0x0000004
2008 #define	EMLXS_TIMER_ENDED	0x0000008
2009 
2010 	/* Misc Timers */
2011 	uint32_t	linkup_timer;
2012 	uint32_t	discovery_timer;
2013 	uint32_t	pkt_timer;
2014 
2015 	/* Power Management */
2016 	uint32_t	pm_state;
2017 	/* pm_state */
2018 #define	EMLXS_PM_IN_ATTACH	0x00000001
2019 #define	EMLXS_PM_IN_DETACH	0x00000002
2020 #define	EMLXS_PM_IN_SOL_CB	0x00000010
2021 #define	EMLXS_PM_IN_UNSOL_CB	0x00000020
2022 #define	EMLXS_PM_IN_LINK_RESET	0x00000100
2023 #define	EMLXS_PM_IN_HARD_RESET	0x00000200
2024 #define	EMLXS_PM_SUSPENDED	0x01000000
2025 
2026 	uint32_t	pm_level;
2027 	/* pm_level */
2028 #define	EMLXS_PM_ADAPTER_DOWN	0
2029 #define	EMLXS_PM_ADAPTER_UP	1
2030 
2031 	uint32_t	pm_busy;
2032 	kmutex_t	pm_lock;
2033 	uint8_t		pm_config[PCI_CONFIG_SIZE];
2034 #ifdef IDLE_TIMER
2035 	uint32_t	pm_idle_timer;
2036 	uint32_t	pm_active;	/* Only used by timer */
2037 #endif	/* IDLE_TIMER */
2038 
2039 	/* Loopback management */
2040 	uint32_t	loopback_tics;
2041 	void		*loopback_pkt;
2042 
2043 	/* Event management */
2044 	emlxs_event_queue_t event_queue;
2045 	uint32_t	event_mask;
2046 	uint32_t	event_timer;
2047 	emlxs_dfc_event_t dfc_event[MAX_DFC_EVENTS];
2048 	emlxs_hba_event_t hba_event;
2049 
2050 	/* Parameter management */
2051 	emlxs_config_t	config[NUM_CFG_PARAM];
2052 
2053 	/* Driver stat management */
2054 	kstat_t		*kstat;
2055 	emlxs_stats_t	stats;
2056 
2057 	/* Log management */
2058 	emlxs_msg_log_t	log;
2059 
2060 	/* Port managment */
2061 	uint32_t	vpi_max;
2062 	uint32_t	vpi_high;
2063 	uint32_t	num_of_ports;
2064 
2065 	kmutex_t	port_lock;	/* locks port, nodes, rings */
2066 	emlxs_port_t	port[MAX_VPORTS + 1];	/* port specific info */
2067 						/* Last one is for */
2068 						/* NPIV ready test */
2069 
2070 #ifdef DHCHAP_SUPPORT
2071 	kmutex_t	dhc_lock;
2072 	kmutex_t	auth_lock;
2073 	emlxs_auth_cfg_t	auth_cfg;	/* Default auth_cfg. */
2074 						/* Points to list of entries. */
2075 						/* Protected by auth_lock */
2076 	uint32_t	auth_cfg_count;
2077 	emlxs_auth_key_t	auth_key;	/* Default auth_key. */
2078 						/* Points to list of entries. */
2079 						/* Protected by auth_lock */
2080 	uint32_t	auth_key_count;
2081 	uint32_t	rdn_flag;
2082 #endif	/* DHCHAP_SUPPORT */
2083 
2084 #ifdef TEST_SUPPORT
2085 	uint32_t	underrun_counter;
2086 #endif /* TEST_SUPPORT */
2087 
2088 #ifdef MODFW_SUPPORT
2089 	ddi_modhandle_t	fw_modhandle;
2090 #endif /* MODFW_SUPPORT */
2091 
2092 #ifdef DUMP_SUPPORT
2093 	emlxs_file_t	dump_txtfile;
2094 	emlxs_file_t	dump_dmpfile;
2095 	emlxs_file_t	dump_ceefile;
2096 	kmutex_t	dump_lock;
2097 #define	EMLXS_DUMP_LOCK		hba->dump_lock
2098 #define	EMLXS_TXT_FILE		1
2099 #define	EMLXS_DMP_FILE		2
2100 #define	EMLXS_CEE_FILE		3
2101 
2102 #define	EMLXS_DRV_DUMP		0
2103 #define	EMLXS_TEMP_DUMP		1
2104 #define	EMLXS_USER_DUMP		2
2105 
2106 #endif /* DUMP_SUPPORT */
2107 
2108 	uint32_t	reset_request;
2109 #define	FC_LINK_RESET		1
2110 #define	FC_PORT_RESET		2
2111 
2112 	uint32_t	reset_state;
2113 #define	FC_LINK_RESET_INP		1
2114 #define	FC_PORT_RESET_INP		2
2115 
2116 } emlxs_hba_t;
2117 
2118 #define	EMLXS_SLI_MAP_HDW 		(hba->sli_api.sli_map_hdw)
2119 #define	EMLXS_SLI_UNMAP_HDW		(hba->sli_api.sli_unmap_hdw)
2120 #define	EMLXS_SLI_ONLINE		(hba->sli_api.sli_online)
2121 #define	EMLXS_SLI_OFFLINE		(hba->sli_api.sli_offline)
2122 #define	EMLXS_SLI_HBA_RESET		(hba->sli_api.sli_hba_reset)
2123 #define	EMLXS_SLI_HBA_KILL		(hba->sli_api.sli_hba_kill)
2124 #define	EMLXS_SLI_ISSUE_IOCB_CMD	(hba->sli_api.sli_issue_iocb_cmd)
2125 #define	EMLXS_SLI_ISSUE_MBOX_CMD	(hba->sli_api.sli_issue_mbox_cmd)
2126 #define	EMLXS_SLI_PREP_FCT_IOCB		(hba->sli_api.sli_prep_fct_iocb)
2127 #define	EMLXS_SLI_PREP_FCP_IOCB		(hba->sli_api.sli_prep_fcp_iocb)
2128 #define	EMLXS_SLI_PREP_IP_IOCB		(hba->sli_api.sli_prep_ip_iocb)
2129 #define	EMLXS_SLI_PREP_ELS_IOCB		(hba->sli_api.sli_prep_els_iocb)
2130 #define	EMLXS_SLI_PREP_CT_IOCB		(hba->sli_api.sli_prep_ct_iocb)
2131 #define	EMLXS_SLI_POLL_INTR		(hba->sli_api.sli_poll_intr)
2132 #define	EMLXS_SLI_INTX_INTR		(hba->sli_api.sli_intx_intr)
2133 #define	EMLXS_SLI_MSI_INTR		(hba->sli_api.sli_msi_intr)
2134 #define	EMLXS_SLI_DISABLE_INTR		(hba->sli_api.sli_disable_intr)
2135 #define	EMLXS_SLI_TIMER			(hba->sli_api.sli_timer)
2136 #define	EMLXS_SLI_POLL_ERRATT		(hba->sli_api.sli_poll_erratt)
2137 #define	EMLXS_SLI_REG_DID		(hba->sli_api.sli_reg_did)
2138 #define	EMLXS_SLI_UNREG_NODE		(hba->sli_api.sli_unreg_node)
2139 
2140 #define	EMLXS_HBA_T  1  /* flag emlxs_hba_t is already typedefed */
2141 
2142 #ifdef MSI_SUPPORT
2143 #define	EMLXS_INTR_INIT(_hba, _m)		emlxs_msi_init(_hba, _m)
2144 #define	EMLXS_INTR_UNINIT(_hba)			emlxs_msi_uninit(_hba)
2145 #define	EMLXS_INTR_ADD(_hba)			emlxs_msi_add(_hba)
2146 #define	EMLXS_INTR_REMOVE(_hba)			emlxs_msi_remove(_hba)
2147 #else
2148 #define	EMLXS_INTR_INIT(_hba, _m)		emlxs_intx_init(_hba, _m)
2149 #define	EMLXS_INTR_UNINIT(_hba)			emlxs_intx_uninit(_hba)
2150 #define	EMLXS_INTR_ADD(_hba)			emlxs_intx_add(_hba)
2151 #define	EMLXS_INTR_REMOVE(_hba)			emlxs_intx_remove(_hba)
2152 #endif	/* MSI_SUPPORT */
2153 
2154 
2155 /* Power Management Component */
2156 #define	EMLXS_PM_ADAPTER	0
2157 
2158 
2159 #define	DRV_TIME	(uint32_t)(ddi_get_time() - emlxs_device.drv_timestamp)
2160 
2161 #define	HBA			port->hba
2162 #define	PPORT			hba->port[0]
2163 #define	VPORT(x)		hba->port[x]
2164 #define	EMLXS_TIMER_LOCK	hba->timer_lock
2165 #define	VPD			hba->vpd
2166 #define	CFG			hba->config[0]
2167 #define	LOG			hba->log
2168 #define	EVENTQ			hba->event_queue
2169 #define	EMLXS_MBOX_LOCK		hba->mbox_lock
2170 #define	EMLXS_MBOX_CV		hba->mbox_lock_cv
2171 #define	EMLXS_LINKUP_LOCK	hba->linkup_lock
2172 #define	EMLXS_LINKUP_CV		hba->linkup_lock_cv
2173 #define	EMLXS_TX_CHANNEL_LOCK	hba->channel_tx_lock	/* ring txq lock */
2174 #define	EMLXS_MEMGET_LOCK	hba->memget_lock	/* mempool get lock */
2175 #define	EMLXS_MEMPUT_LOCK	hba->memput_lock	/* mempool put lock */
2176 #define	EMLXS_IOCTL_LOCK	hba->ioctl_lock		/* ioctl lock */
2177 #define	EMLXS_SPAWN_LOCK	hba->spawn_lock		/* spawn lock */
2178 #define	EMLXS_PM_LOCK		hba->pm_lock		/* pm lock */
2179 #define	HBASTATS		hba->stats
2180 #define	EMLXS_CMD_RING_LOCK(n)	hba->sli.sli3.ring_cmd_lock[n]
2181 
2182 #define	EMLXS_QUE_LOCK(n)	hba->sli.sli4.que_lock[n]
2183 #define	EMLXS_MSIID_LOCK	hba->msiid_lock
2184 
2185 #define	EMLXS_FCTAB_LOCK	hba->iotag_lock
2186 
2187 #define	EMLXS_FCF_LOCK		hba->sli.sli4.fcf_lock
2188 
2189 #define	EMLXS_PORT_LOCK		hba->port_lock		/* locks ports, */
2190 							/* nodes, rings */
2191 #define	EMLXS_INTR_LOCK(_id)	hba->intr_lock[_id]	/* locks intr threads */
2192 
2193 #define	EMLXS_PKT_LOCK		port->pkt_lock		/* used for pkt */
2194 							/* polling */
2195 #define	EMLXS_PKT_CV		port->pkt_lock_cv	/* Used for pkt */
2196 							/* polling */
2197 #define	EMLXS_UB_LOCK		port->ub_lock		/* locks unsolicited */
2198 							/* buffer pool */
2199 
2200 /* These SWAPs will swap on any platform */
2201 #define	SWAP32_BUFFER(_b, _c)		emlxs_swap32_buffer(_b, _c)
2202 #define	SWAP32_BCOPY(_s, _d, _c)	emlxs_swap32_bcopy(_s, _d, _c)
2203 
2204 #define	SWAP64(_x)	((((uint64_t)(_x) & 0xFF)<<56) | \
2205 			    (((uint64_t)(_x) & 0xFF00)<<40) | \
2206 			    (((uint64_t)(_x) & 0xFF0000)<<24) | \
2207 			    (((uint64_t)(_x) & 0xFF000000)<<8) | \
2208 			    (((uint64_t)(_x) & 0xFF00000000)>>8) | \
2209 			    (((uint64_t)(_x) & 0xFF0000000000)>>24) | \
2210 			    (((uint64_t)(_x) & 0xFF000000000000)>>40) | \
2211 			    (((uint64_t)(_x) & 0xFF00000000000000)>>56))
2212 
2213 #define	SWAP32(_x)	((((uint32_t)(_x) & 0xFF)<<24) | \
2214 			    (((uint32_t)(_x) & 0xFF00)<<8) | \
2215 			    (((uint32_t)(_x) & 0xFF0000)>>8) | \
2216 			    (((uint32_t)(_x) & 0xFF000000)>>24))
2217 
2218 #define	SWAP16(_x)	((((uint16_t)(_x) & 0xFF)<<8) | \
2219 			    (((uint16_t)(_x) & 0xFF00)>>8))
2220 
2221 #define	SWAP24_LO(_x)	((((uint32_t)(_x) & 0xFF)<<16) | \
2222 			    ((uint32_t)(_x) & 0xFF00FF00) | \
2223 			    (((uint32_t)(_x) & 0x00FF0000)>>16))
2224 
2225 #define	SWAP24_HI(_x)	(((uint32_t)(_x) & 0x00FF00FF) | \
2226 			    (((uint32_t)(_x) & 0x0000FF00)<<16) | \
2227 			    (((uint32_t)(_x) & 0xFF000000)>>16))
2228 
2229 /* These LE_SWAPs will only swap on a LE platform */
2230 #ifdef EMLXS_LITTLE_ENDIAN
2231 #define	LE_SWAP32_BUFFER(_b, _c)	SWAP32_BUFFER(_b, _c)
2232 #define	LE_SWAP32_BCOPY(_s, _d, _c)	SWAP32_BCOPY(_s, _d, _c)
2233 #define	LE_SWAP64(_x)			SWAP64(_x)
2234 #define	LE_SWAP32(_x)			SWAP32(_x)
2235 #define	LE_SWAP16(_x)			SWAP16(_x)
2236 #define	LE_SWAP24_LO(_x)		SWAP24_LO(X)
2237 #define	LE_SWAP24_HI(_x)		SWAP24_HI(X)
2238 
2239 #if (EMLXS_MODREVX == EMLXS_MODREV2X)
2240 #undef	LE_SWAP24_LO
2241 #define	LE_SWAP24_LO(_x)		(_x)
2242 #undef	LE_SWAP24_HI
2243 #define	LE_SWAP24_HI(_x)		(_x)
2244 #endif	/* EMLXS_MODREV2X */
2245 
2246 #else /* BIG ENDIAN */
2247 #define	LE_SWAP32_BUFFER(_b, _c)
2248 #define	LE_SWAP32_BCOPY(_s, _d, _c)	bcopy(_s, _d, _c)
2249 #define	LE_SWAP64(_x)			(_x)
2250 #define	LE_SWAP32(_x)			(_x)
2251 #define	LE_SWAP16(_x)			(_x)
2252 #define	LE_SWAP24_LO(_x)		(_x)
2253 #define	LE_SWAP24_HI(_x)		(_x)
2254 #endif /* EMLXS_LITTLE_ENDIAN */
2255 
2256 /* These BE_SWAPs will only swap on a BE platform */
2257 #ifdef EMLXS_BIG_ENDIAN
2258 #define	BE_SWAP32_BUFFER(_b, _c)	SWAP32_BUFFER(_b, _c)
2259 #define	BE_SWAP32_BCOPY(_s, _d, _c)	SWAP32_BCOPY(_s, _d, _c)
2260 #define	BE_SWAP64(_x)			SWAP64(_x)
2261 #define	BE_SWAP32(_x)			SWAP32(_x)
2262 #define	BE_SWAP16(_x)			SWAP16(_x)
2263 #else /* LITTLE ENDIAN */
2264 #define	BE_SWAP32_BUFFER(_b, _c)
2265 #define	BE_SWAP32_BCOPY(_s, _d, _c)	bcopy(_s, _d, _c)
2266 #define	BE_SWAP64(_x)			(_x)
2267 #define	BE_SWAP32(_x)			(_x)
2268 #define	BE_SWAP16(_x)			(_x)
2269 #endif /* EMLXS_BIG_ENDIAN */
2270 
2271 #define	EMLXS_DFC_RESET_ALL			0x10
2272 #define	EMLXS_DFC_RESET_ALL_FORCE_DUMP		0x11
2273 
2274 #ifdef	__cplusplus
2275 }
2276 #endif
2277 
2278 #endif	/* _EMLXS_FC_H */
2279