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Searched refs:ESR_N2_PLL_REG_OFFSET (Results 1 – 1 of 1) sorted by relevance

/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_n2_esr_hw.h41 #define ESR_N2_PLL_REG_OFFSET 0 macro
65 #define ESR_N2_PLL_CFG_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET
66 #define ESR_N2_PLL_CFG_L_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET
67 #define ESR_N2_PLL_CFG_H_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 1
68 #define ESR_N2_PLL_STS_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 2
69 #define ESR_N2_PLL_STS_L_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 2
70 #define ESR_N2_PLL_STS_H_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 3