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Searched refs:DR_MEM_RES_EFAULT (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/sun4v/sys/
H A Ddr_mem.h91 #define DR_MEM_RES_EFAULT 0x5 /* memory access test failed */ macro
/titanic_41/usr/src/uts/sun4v/io/
H A Ddr_mem.c832 rv = DR_MEM_RES_EFAULT; in cvt_err()