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Searched refs:DRM_COMMAND_BASE (Results 1 – 4 of 4) sorted by relevance

/titanic_41/usr/src/uts/intel/io/drm/
H A Di915_drm.h196 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
197 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
198 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
199 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batch…
200 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq…
201 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq…
202 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_get…
203 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_set…
204 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_al…
205 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_fre…
[all …]
H A Dradeon_drm.h501 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
503 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START)
505 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
507 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
509 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
511 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET)
513 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, \
516 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP)
518 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
520 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
[all …]
/titanic_41/usr/src/uts/common/io/drm/
H A Ddrm_sunmod.c473 if (ioctl->func == NULL && nr >= DRM_COMMAND_BASE) { in drm_sun_ioctl()
475 nr -= DRM_COMMAND_BASE; in drm_sun_ioctl()
H A Ddrm.h862 #define DRM_COMMAND_BASE 0x40 macro