| /titanic_41/usr/src/uts/sparc/sys/ |
| H A D | machlock.h | 104 #define DISP_LEVEL (LOCK_LEVEL + 1) macro
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| /titanic_41/usr/src/uts/intel/sys/ |
| H A D | machlock.h | 113 #define DISP_LEVEL (LOCK_LEVEL + 1) macro
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| /titanic_41/usr/src/uts/i86pc/ml/ |
| H A D | genassym.c | 75 printf("#define\tDISP_LEVEL 0x%x\n", DISP_LEVEL); in main()
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| /titanic_41/usr/src/uts/common/disp/ |
| H A D | disp_lock.c | 88 lock_set_spl(lp, ipltospl(DISP_LEVEL), &curthread->t_oldspl); in disp_lock_enter()
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| H A D | fx.c | 1836 return ((void *)(uintptr_t)__ipltospl(DISP_LEVEL)); in fx_get_mutex_cookie()
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| H A D | thread.c | 175 mutex_init(&reaplock, NULL, MUTEX_SPIN, (void *)ipltospl(DISP_LEVEL)); in thread_init()
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| H A D | disp.c | 1037 ASSERT(getpil() >= DISP_LEVEL); in thread_on_queue()
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| /titanic_41/usr/src/uts/i86pc/os/ |
| H A D | pci_cfgspace.c | 113 (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL)); in pci_cfgspace_init()
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| H A D | trap.c | 1638 if (getpil() >= DISP_LEVEL) { in kpreempt()
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| /titanic_41/usr/src/uts/common/os/ |
| H A D | softint.c | 216 ASSERT(getpil() >= DISP_LEVEL); in softcall_choose_cpu()
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| H A D | cpu.c | 549 getpil() >= DISP_LEVEL) { in thread_nomigrate()
682 getpil() >= DISP_LEVEL); in thread_allowmigrate()
685 getpil() >= DISP_LEVEL) in thread_allowmigrate()
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| /titanic_41/usr/src/uts/sun4/ml/ |
| H A D | interrupt.s | 145 ! intr_thread starts at DISP_LEVEL to prevent preemption
153 mov DISP_LEVEL, %g4 ! %g4 = DISP_LEVEL (11)
565 wrpr %g0, DISP_LEVEL, %pil
697 wrpr %g0, DISP_LEVEL, %pil ! up from cpu_base_spl
807 ! All traps below DISP_LEVEL are disabled here, but the mondo interrupt
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| /titanic_41/usr/src/uts/intel/ia32/os/ |
| H A D | desctbls.c | 1316 ASSERT(curthread->t_preempt != 0 || getpil() >= DISP_LEVEL); in brand_interpositioning_enable()
1362 ASSERT(curthread->t_preempt != 0 || getpil() >= DISP_LEVEL); in brand_interpositioning_disable()
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| H A D | sundep.c | 651 ASSERT(curthread->t_preempt != 0 || getpil() >= DISP_LEVEL); in reset_sregs()
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| /titanic_41/usr/src/uts/intel/io/acpica/ |
| H A D | acpica.c | 148 (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL)); in _init()
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| /titanic_41/usr/src/uts/sun4v/pcbe/ |
| H A D | niagara2_pcbe.c | 424 ASSERT(getpil() >= DISP_LEVEL); in ni2_pcbe_overflow_bitmap()
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| /titanic_41/usr/src/uts/sparc/v9/ml/ |
| H A D | sparcv9_subr.s | 216 RAISE_HIGH(DISP_LEVEL)
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| /titanic_41/usr/src/uts/sparc/dtrace/ |
| H A D | dtrace_isa.c | 341 dtrace_getipl() > DISP_LEVEL); in dtrace_getpcstack()
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| /titanic_41/usr/src/uts/i86pc/os/cpupm/ |
| H A D | cpupm_mach.c | 504 (void *)ipltospl(DISP_LEVEL)); in cpupm_alloc_domains()
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| /titanic_41/usr/src/uts/sun4/os/ |
| H A D | trap.c | 1875 getpil()) >= DISP_LEVEL) { in kpreempt()
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| /titanic_41/usr/src/uts/intel/ia32/ml/ |
| H A D | i86_subr.s | 1210 RAISE(DISP_LEVEL)
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| /titanic_41/usr/src/uts/sun4u/cpu/ |
| H A D | us3_common.c | 3005 ASSERT(curthread->t_preempt > 0 || getpil() >= DISP_LEVEL); in ce_ptnr_select()
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| /titanic_41/usr/src/uts/sfmmu/vm/ |
| H A D | hat_sfmmu.c | 1626 (void *)ipltospl(DISP_LEVEL)); in sfmmu_cpu_init()
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