Searched refs:DCFG_S4 (Results 1 – 2 of 2) sorted by relevance
| /titanic_41/usr/src/uts/intel/io/mc-amd/ |
| H A D | mcamd_dimmcfg.c | 238 { AM2, 2, DCFG_S4, 0, { { CH_A, 1, 0 }, { CH_B, 1, 0 } } },
240 { S1g1, 2, DCFG_S4, 0, { { CH_A, 0, 2 }, { CH_B, 0, 2 } } },
245 { AM2, 3, DCFG_S4, 0, { { CH_A, 1, 1 }, { CH_B, 1, 1 } } },
247 { S1g1, 3, DCFG_S4, 0, { { CH_A, 0, 3 }, { CH_B, 0, 3 } } },
281 { AM2S1g1, 0, DCFG_N | DCFG_S4, 0, { { CH_A, 0, 0 } } },
285 { AM2S1g1, 1, DCFG_N | DCFG_S4, 0, { { CH_A, 0, 1 } } },
290 { AM2, 2, DCFG_S4, 0, { { CH_A, 1, 0 } } },
292 { S1g1, 2, DCFG_S4, 0, { { CH_A, 0, 2 } } },
297 { AM2, 3, DCFG_S4, 0, { { CH_A, 1, 1 } } },
299 { S1g1, 3, DCFG_S4, 0, { { CH_A, 0, 3 } } },
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| H A D | mcamd_dimmcfg_impl.h | 81 #define DCFG_S4 0x4 /* four-rank SO-DIMM (NPT only) */ macro
83 #define DCFG_ALLNPT (DCFG_N | DCFG_R4 | DCFG_S4)
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