1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 1999-2003 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SCAT_DCD_H 28 #define _SCAT_DCD_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * This file contains definitions of the structures gdcd_t and ldcd_t, 34 * Global and Local Domain Configuration Descriptors and the various 35 * substructures they contain. 36 * The gdcd is the information handed off to OBP and the OS by POST 37 * in the "golden" I/O SRAM of a domain in Sun Fire 15000 systems. 38 * The ldcd contains information about the two ports local to each 39 * sram, kept in that local sram, to support DR operations. 40 */ 41 42 #include <sys/types.h> 43 44 #include <post/scat_const.h> 45 #include <post/scat_asicbrd_types.h> 46 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 #define DCD_VERSION 4 53 54 55 #define GDCD_MAGIC (('G'<< 24) | ('D'<< 16) | ('C'<< 8) | 'D') 56 #define LDCD_MAGIC (('L'<< 24) | ('D'<< 16) | ('C'<< 8) | 'D') 57 58 59 #define PMBANKS_PER_PORT 2 60 #define LMBANKS_PER_PMBANK 2 61 #define IOBUS_PER_PORT 2 62 #define IOCARD_PER_BUS 4 /* 1 currently, but could change */ 63 #define LINKS_PER_PORT 5 /* 3 in current hardware */ 64 #define DIMMS_PER_PORT 8 65 #define DIMMS_PER_PMBANK 4 66 #define ECDIMMS_PER_PORT 2 67 68 /* 69 * This is intended to handle Jubatus8X - up to 8 CPU cores 70 * within one Safari port. 71 */ 72 #define SAF_AGENT_PER_PORT 8 73 74 /* 75 * The most significant element of the otherwise unused 76 * prd_t.prd_wic_links[LINKS_PER_PORT] in processor ports is 77 * reserved for use by DR to save the prd_prsv of the port 78 * while that is temporarily marked RSV_UNCONFIG when the 79 * processor is borrowed for I/O cage testing for DR. 80 * It is expected that .prd_wic_links[PRD_LINK_IX_HOLD_CPUPORT_PRSV] 81 * will be restored to RSV_UNDEFINED when the prd_prsv is 82 * restored to its original value. It would be a Good Thing to 83 * check that prd_prsv is not ever being set to RSV_UNDEFINED; 84 * it's probably wrong to restore it to other than RSV_GOOD(). 85 */ 86 #define PRD_LINK_IX_HOLD_CPUPORT_PRSV (LINKS_PER_PORT - 1) 87 88 /* 89 * There are four Address Decode Registers, 0 - 3, one for each 90 * logical bank. ADR 0 and 2 control the logical banks in 91 * physical bank 0; ADR 1 and 3 control the logical banks in 92 * physical bank 1. 93 */ 94 #define ADR2PBANK(adr) ((adr) & 1) 95 #define ADR2LBANK(adr) (((adr) >> 1) & 1) 96 #define PLBANK2ADR(pbank, lbank) ((((lbank) & 1) << 1) | ((pbank) & 1)) 97 98 99 /* ======================================================== */ 100 /* 101 * RSV stands for Resource Status Value. 102 * These are the values used in all cases where the status of 103 * a resource is maintained in a byte element of a structure. 104 * These are ordered in terms of preserving interesting information 105 * in POST displays where all configurations are displayed in a 106 * single value. The highest value for a resource over all 107 * configurations is shown. 108 * Of course, this is just for help to engineers/technicians in 109 * understanding what happened; for the most part, everything 110 * except "GOOD" is just different flavors of "BAD". 111 * This is not an enum because they need to fit in a byte. 112 */ 113 114 typedef uint8_t prdrsv_t; 115 116 #define RSV_UNKNOWN 0x0 /* No status yet */ 117 #define RSV_PRESENT 0x1 /* Presence detected */ 118 #define RSV_CRUNCH 0x2 /* Unusable by implication */ 119 #define RSV_UNDEFINED 0x3 /* Architecturally Missing */ 120 #define RSV_MISS 0x4 /* Missing */ 121 #define RSV_MISCONFIG 0x5 /* Misconfigured, e.g., mixed dimms */ 122 #define RSV_FAIL_OBP 0x6 /* Failed by OBP */ 123 #define RSV_FAIL 0x7 /* Tested and failed */ 124 #define RSV_BLACK 0x8 /* Blacklisted */ 125 #define RSV_RED 0x9 /* Redlisted */ 126 #define RSV_EXCLUDED 0xA /* Not in this domain */ 127 #define RSV_UNCONFIG 0xB /* Good, but not in config. */ 128 #define RSV_PASS 0xC /* Passed some sort of test; */ 129 /* Always subject to more... */ 130 /* 131 * Odd proc of a good Lockstep pair. Valid only for prd_prsv for 132 * processor ports. 133 */ 134 #define RSV_LOCKSTEP 0xD 135 136 /* 137 * This will be used instead of RSV_MISS when an hsPCI 138 * cassette is present but it contains no PCI adapter. 139 * Intended to be used only for prd_t.prd_iocard_rsv[][] 140 */ 141 #define RSV_EMPTY_CASSETTE 0xF /* An hsPCI cassette, no adapter */ 142 143 /* 144 * This definition of Good depends on context. 145 * Some customers of this status may want to use only PASS. 146 */ 147 #define RSV_GOOD(rsv) \ 148 (RSV_PASS == (rsv) || RSV_UNKNOWN == (rsv) || RSV_PRESENT == (rsv)) 149 150 #define RSV_NOTOUCH(rsv) (RSV_EXCLUDED == (rsv) || RSV_RED == (rsv)) 151 152 /* ============================================================ */ 153 /* Port Resource Descriptor - PRD */ 154 155 typedef struct { 156 uint64_t prd_ver_reg; /* port version register */ 157 /* 158 * For ports with memory, the address decode register 159 * for each bank, and the address control register. 160 */ 161 uint64_t prd_madr[PMBANKS_PER_PORT][LMBANKS_PER_PMBANK]; 162 uint64_t prd_macr; 163 /* DOUBLEWORD */ 164 165 uint16_t prd_rfreq; /* rated frequency Mhz */ 166 uint16_t prd_afreq_ratio; /* ratio of actual frequency */ 167 /* to interconnect speed */ 168 169 prdrsv_t prd_prsv; /* status of entire port. */ 170 uint8_t prd_ptype; /* port type. See SAFPTYPE_ below */ 171 172 /* memory configuration state */ 173 uint8_t prd_mem_config_state; 174 175 uint8_t prd_fill1; 176 /* DOUBLEWORD */ 177 178 /* 179 * This is intended to handle Jubatus2X - 8X. 180 * For all other cases, expect that prd_agent[0] = prd_prsv, 181 * and prd_agent[7:1] = RSV_UNDEFINED. 182 * For JubatusnX, it conveys the status of the 183 * n core processors. 184 */ 185 prdrsv_t prd_agent[SAF_AGENT_PER_PORT]; 186 /* DOUBLEWORD */ 187 188 /* for ports that have memory */ 189 prdrsv_t prd_bank_rsv[PMBANKS_PER_PORT][LMBANKS_PER_PMBANK]; 190 /* bank rsv */ 191 uint16_t prd_log_bank_size[PMBANKS_PER_PORT]; /* bank size */ 192 /* 193 * If a physical bank has two logical 194 * banks, they are always the same size. 195 */ 196 /* DOUBLEWORD */ 197 198 /* for ports with IO buses */ 199 prdrsv_t prd_iocard_rsv[IOBUS_PER_PORT][IOCARD_PER_BUS]; 200 /* 201 * Currently, only 1 adapter is on each bus and index 202 * zero is used for that. Index 1 is reserved. 203 * The remaining 2 are used to support in-kernel-probing, 204 * to avoid board specific hooks. 205 * They only exist on bus 1 of Schizo 0 on the board. 206 */ 207 #define IOBOARD_BBCRIO_PORT 0 208 #define IOBOARD_BBCRIO_BUS 1 209 #define IOCARD_RSV_SBBC_INDEX 2 210 #define IOCARD_RSV_RIO_INDEX 3 211 212 /* DOUBLEWORD */ 213 214 prdrsv_t prd_iobus_rsv[IOBUS_PER_PORT]; 215 216 /* For ports with WCI links, status of each link */ 217 prdrsv_t prd_wic_links[LINKS_PER_PORT]; 218 219 uint8_t fill2; 220 /* DOUBLEWORD */ 221 222 223 prdrsv_t prd_dimm[PMBANKS_PER_PORT][DIMMS_PER_PMBANK]; 224 /* 225 * Status for dimms [1:0][3:0]. 226 * This contains at most only probing information. 227 * Testing is done on logical banks, so results are 228 * not representable at the dimm level, since each 229 * dimm contains part of two logical banks. 230 * 231 * Also, probing is expensive in time, so it is 232 * skipped if the results would not affect available 233 * resources. 234 * Example: if dimm 0 of a pbank is missing, the other 235 * three dimms are ignored and will be RSV_UNKNOWN. 236 */ 237 238 /* DOUBLEWORD */ 239 uint8_t prd_cache; /* external cache size (MByte) */ 240 prdrsv_t prd_ecdimm[ECDIMMS_PER_PORT]; 241 /* status for ecache dimms 0..1 */ 242 243 244 uint8_t prd_sparebyte[5]; 245 /* DOUBLEWORD */ 246 uint32_t prd_spare[4]; 247 /* DOUBLEWORD */ 248 249 } prd_t; 250 251 /* prd_mem_config_state manifest constants */ 252 #define PRD_MCS_BANKS ((uint8_t)1 << 0) 253 #define PRD_MCS_SLICE ((uint8_t)1 << 1) 254 #define PRD_MCS_IMODE(mode) (((uint8_t)(mode) & 0x3) << 2) 255 #define PRD_MCS_GET_IMODE(mcs) (((uint8_t)(mcs) & 0xC) >> 2) 256 #define PRD_MCS_FAILD ((uint8_t)1 << 6) 257 #define PRD_MCS_VALID ((uint8_t)1 << 7) 258 259 260 /* Types of Safari ports. Not an enum so it fits in a byte. */ 261 #define SAFPTYPE_NULL 0 262 #define SAFPTYPE_CPU 1 263 #define SAFPTYPE_sPCI 2 264 #define SAFPTYPE_cPCI 3 265 #define SAFPTYPE_WCI 4 266 #define SAFPTYPE_PCIX 5 267 #define SAFPTYPE_MAX SAFPTYPE_PCIX 268 269 #define SAFTYPE_PCI(type) \ 270 ((SAFPTYPE_sPCI == (type)) || (SAFPTYPE_cPCI == (type))) 271 272 273 /* ======================================================== */ 274 /* Local and Global Domain Configuration Descriptors LDCD & GDCD */ 275 276 /* Enumeration of process types for xdcd.h.dcd_lmod_type */ 277 typedef enum { 278 DCDLMT_OTHER, /* Something not otherwise in this enum */ 279 DCDLMT_POST_BOOT, /* POST at initial domain creation */ 280 DCDLMT_POST_DR, /* POST for some sort of DR case */ 281 DCDLMT_OBP, /* Domain Open Boot */ 282 DCDLMT_OS, /* Domain Solaris */ 283 DCDLMT_DR_SMS, /* DR process running on SSC */ 284 DCDLMT_DR_DOMAIN, /* DR process running on domain */ 285 DCDLMT_OTHER_SMS, /* Non-DR process running on SSC */ 286 DCDLMT_COUNT /* Array size for strings, etc. */ 287 } dcd_lmod_type_t; 288 289 290 /* dcd substructure for status of L1 boards in each slot */ 291 typedef struct { 292 xcl1bt_t l1ss_type; /* enum in scat_asicbrd_types.h */ 293 prdrsv_t l1ss_rsv; /* Status. */ 294 /* 295 * The cdc information is rightfully 296 * only relevant to the EXB and the 297 * slot 0 board of that EXB. But it 298 * needs to stay with that slot 0 299 * board over DR operations, so 300 * it goes here. 301 * It should be ignored for slot 1 302 * boards. 303 */ 304 prdrsv_t l1ss_cdc_rsv; 305 uint8_t l1ss_cdc_dimm_size; /* MBytes */ 306 uint8_t l1ss_fill1; /* Explicit alignment */ 307 /* DOUBLEWORD */ 308 /* 309 * So Starcat software that doesn't 310 * have knowledge of the CPU sram 311 * TOC format can find the LDCD in 312 * CPU srams. 313 */ 314 uint16_t l1ss_cpu_ldcd_xwd_offset; /* Byte offset >> 3 */ 315 uint16_t l1ss_cpu_drblock_xwd_offset; /* Byte offset >> 3 */ 316 uint8_t l1ss_flags; /* See below */ 317 uint8_t l1ss_sparebyte[3]; 318 uint32_t l1ss_spare[2]; 319 /* DOUBLEWORD */ 320 } l1_slot_stat_t; 321 322 /* 323 * When this flag is set, all CPUs on this L1 board should be 324 * configured with a NULL Local Physical Address (LPA) range in 325 * their Safari Config Registers. 326 * This flag can be ignored for boards with no processors. 327 */ 328 #define L1SSFLG_THIS_L1_NULL_PROC_LPA (1 << 0) 329 330 331 /* dcd substructure for memory chunk list. */ 332 typedef struct { 333 uint64_t mc_base_pa; /* Base Physical Address */ 334 uint64_t mc_mbytes; /* Size of Chunk in MBytes */ 335 } mem_chunk_t; 336 337 #define MAX_DOM_MEM_CHUNKS (EXP_COUNT * S0_LPORT_COUNT * \ 338 PMBANKS_PER_PORT * LMBANKS_PER_PMBANK) 339 typedef struct { 340 uint64_t dcl_chunks; /* number of chunks */ 341 mem_chunk_t dcl_chunk[MAX_DOM_MEM_CHUNKS]; 342 } domain_chunk_list_t; 343 344 #define MAX_EXP_MEM_CHUNKS (S0_LPORT_COUNT * \ 345 PMBANKS_PER_PORT * LMBANKS_PER_PMBANK) 346 typedef struct { 347 uint64_t ecl_chunks; /* number of chunks */ 348 mem_chunk_t ecl_chunk[MAX_EXP_MEM_CHUNKS]; 349 } exp_chunk_list_t; 350 351 typedef struct { 352 uint32_t dcd_magic; /* GDCD_MAGIC or LDCD_MAGIC */ 353 uint32_t dcd_version; /* structure version: DCD_VERSION */ 354 uint32_t dcd_csum; /* So sum((uint[]) xdcd) == 0. */ 355 uint32_t dcd_post_pid; /* Process ID of the SSC hpost that */ 356 /* originally created this domain */ 357 /* or POSTed this board. */ 358 /* DOUBLEWORD */ 359 360 uint64_t dcd_boot_time; /* Time of creation of the domain */ 361 /* by POST. To be backward compatible */ 362 /* in ILD32, uint64_t is used instead */ 363 /* of time_t. */ 364 365 uint64_t dcd_lmod_time; /* Time of last modification of */ 366 /* this structure. */ 367 368 uint32_t dcd_lmod_pid; /* Process ID of the last modifier */ 369 /* of this structure. If the last */ 370 /* modifier has no PID, set to 0. */ 371 372 dcd_lmod_type_t dcd_lmod_type; /* Type of process that last modified */ 373 /* this structure. See above. */ 374 /* DOUBLEWORD */ 375 376 uint32_t dcd_mod_count; /* Count of the number of times */ 377 /* this structure has been modified. */ 378 /* Set to 0 by original POST. */ 379 380 uint32_t dcd_post_level; /* Level at which POST executed */ 381 /* for most recent boot or test. */ 382 /* DOUBLEWORD */ 383 384 uint32_t dcd_post_private; /* Private word for POST */ 385 uint32_t dcd_flags; /* See DCDFLAG_xxx */ 386 uint32_t dcd_spare[8]; /* Minimize future problems */ 387 /* DOUBLEWORD */ 388 } dcd_header_t; 389 390 391 /* 392 * This flag is only for use in LDCDs. It is set when this 393 * board is part of a domain and the local DCD is considered 394 * only a secondary copy of the information in the GDCD. 395 * We do not keep the GDCD location here, since that would 396 * impose extra work on DR when the golden IOSRAM board detaches. 397 * POST will set this in all LDCDs in a newly booted domain. 398 */ 399 #define DCDFLAG_IN_DOMAIN (1u << 0) 400 401 /* 402 * This flag is only for use in LDCDs. It is set when this 403 * board was called for hpost -H (h.dcd_lmod_type is DCDLMT_POST_DR) 404 * and no testing was required. All that was done was clearing. 405 */ 406 #define DCDFLAG_CLEARED_ONLY (1u << 1) 407 408 /* POST inititalizes dcd_testcage_mbyte_PA to this value */ 409 #define DCD_TESTCAGE_MBYTE_PA_INIT ((uint32_t)-1) 410 /* 411 * zero (0) in dcd_testcage_log2_mbytes has the special meaning 412 * that no testcage memory is to be allocated. 413 * zero (0) in dcd_testcage_log2_mbytes_align is a real 414 * alignment of 1MB. 415 */ 416 #define DCD_DR_TESTCAGE_DISABLED (0) /* zero size cage */ 417 #define DCD_DR_TESTCAGE_LOG2_1MB_ALIGN (0) /* 2^0 = 1 for */ 418 /* 419 * The remainder of these constants can be used for 420 * either dcd_testcage_* variable and indicate the 421 * value shown. 422 */ 423 #define DCD_DR_TESTCAGE_LOG2_2MB (1) /* 2^1 = 2 */ 424 #define DCD_DR_TESTCAGE_LOG2_4MB (2) /* 2^2 = 4 */ 425 #define DCD_DR_TESTCAGE_LOG2_8MB (3) /* 2^3 = 8 */ 426 #define DCD_DR_TESTCAGE_LOG2_16MB (4) /* 2^4 = 16 */ 427 #define DCD_DR_TESTCAGE_LOG2_32MB (5) /* 2^5 = 32 */ 428 #define DCD_DR_TESTCAGE_LOG2_64MB (6) /* 2^6 = 64 */ 429 #define DCD_DR_TESTCAGE_LOG2_128MB (7) /* 2^7 = 128 */ 430 #define DCD_DR_TESTCAGE_LOG2_256MB (8) /* 2^8 = 256 */ 431 #define DCD_DR_TESTCAGE_LOG2_512MB (9) /* 2^9 = 512 */ 432 #define DCD_DR_TESTCAGE_LOG2_1024MB (10) /* 2^10 = 1024 */ 433 434 /* Global DCD - exists only in golden I/O sram */ 435 typedef struct { 436 dcd_header_t h; 437 /* DOUBLEWORD */ 438 439 uint32_t dcd_intercon_freq; /* In Hertz */ 440 uint8_t dcd_abus_mask; /* Address bus config [1:0] */ 441 uint8_t dcd_dbus_mask; /* Data bus config [1:0] */ 442 uint8_t dcd_rbus_mask; /* Response bus config [1:0] */ 443 uint8_t dcd_stick_ratio; /* Ratio of intercon:STICK */ 444 /* DOUBLEWORD */ 445 446 uint8_t dcd_domain; /* 0-17 or other if unknown */ 447 /* 448 * Specification of the required size and alignment of 449 * the DR testcage memory used during POST -H testcage runs. 450 * The formula is bytes = (1 << (log2_value + 20)). 451 */ 452 uint8_t dcd_testcage_log2_mbytes_size; 453 uint8_t dcd_testcage_log2_mbytes_align; 454 uint8_t dcd_fill[5]; 455 /* DOUBLEWORD */ 456 /* 457 * Specification of the DR testcage memory base physical addr. 458 * This is initialized to DCD_TESTCAGE_PA_INIT by POST 459 * and set by setkeyswitch when it determines the location of 460 * the testcage. The formula is PA = (mbyte_PA << 20). 461 */ 462 uint32_t dcd_testcage_mbyte_PA; 463 uint32_t dcd_spare[3]; /* Avoid future problems */ 464 /* DOUBLEWORD */ 465 466 /* Information on the L1 boards in each slot: */ 467 l1_slot_stat_t dcd_slot[EXP_COUNT][SLOT_COUNT]; 468 /* DOUBLEWORD */ 469 470 /* 471 * Information on 108 Safari ports. 472 * See scat_const.h for macros that will help in computing 473 * indexes into this array, particularly "PWE" and "PFP". 474 */ 475 prd_t dcd_prd[EXP_COUNT][PORT_PER_EXP]; 476 /* DOUBLEWORD */ 477 478 /* 479 * memory chunk list for the domain; max 288 chunks. 480 * This is the worst case scenario where there is no 481 * interleaving and no re-configuration of the memory address 482 * decode registers to make board memory contiguous. 483 * This uses 288 * 16bytes = 4608KB. 484 */ 485 domain_chunk_list_t dcd_chunk_list; 486 } gdcd_t; 487 488 /* Local DCD - exists in every I/O, CPU, and WCI sram */ 489 typedef struct { 490 dcd_header_t h; 491 /* DOUBLEWORD */ 492 493 /* Information on the L1 board in this slot: */ 494 l1_slot_stat_t dcd_slot; 495 /* DOUBLEWORD */ 496 497 /* Information on 2 Safari ports: */ 498 prd_t dcd_prd[2]; 499 /* DOUBLEWORD */ 500 501 /* memory chunk list for this exp; max 16 chunks */ 502 exp_chunk_list_t dcd_chunk_list; 503 } ldcd_t; 504 505 #ifdef __cplusplus 506 } 507 #endif 508 509 #endif /* !_SCAT_DCD_H */ 510