xref: /titanic_41/usr/src/uts/common/sys/1394/targets/dcam1394/dcam_reg.h (revision 8eea8e29cc4374d1ee24c25a07f45af132db3499)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_1394_TARGETS_DCAM1394_REG_H
28 #define	_SYS_1394_TARGETS_DCAM1394_REG_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #include <sys/1394/targets/dcam1394/dcam.h>
33 
34 #ifdef	__cplusplus
35 extern "C" {
36 #endif
37 
38 /*
39  * dcam spec: Sec 1.1 Camera Initialize Register
40  */
41 #define	DCAM1394_REG_OFFS_INITIALIZE		0x0
42 #define	DCAM1394_REG_VAL_INITIALIZE_ASSERT	0x80000000
43 
44 /*
45  * dcam spec: Sec 1.2.1.1 Inquiry Register for Video Mode
46  */
47 #define	DCAM1394_REG_OFFS_VID_MODE_INQ		0x180
48 
49 /*
50  * dcam spec: Sec 1.2.2 Inquiry Register for Video Frame Rate
51  */
52 #define	DCAM1394_REG_OFFS_FRAME_RATE_INQ_BASE	0x200
53 
54 /*
55  * dcam spec: basic function inquiry registers, sec 1.3
56  */
57 #define	DCAM1394_REG_OFFS_BASIC_FUNC_INQ	0x400
58 
59 #define	DCAM1394_MASK_CAM_POWER_CTRL		0x8000
60 #define	DCAM1394_SHIFT_CAM_POWER_CTRL		15
61 
62 
63 /*
64  * dcam spec: Sec 1.5 Inquiry Register for Feature Elements
65  */
66 #define	DCAM1394_REG_OFFS_FEATURE_ELM_INQ_BASE  0x500
67 
68 #define	DCAM1394_REG_OFFS_BRIGHTNESS_INQ	0x0
69 #define	DCAM1394_REG_OFFS_EXPOSURE_INQ		0x4
70 #define	DCAM1394_REG_OFFS_SHARPNESS_INQ		0x8
71 #define	DCAM1394_REG_OFFS_WHITE_BALANCE_INQ	0xC
72 #define	DCAM1394_REG_OFFS_HUE_INQ		0x10
73 #define	DCAM1394_REG_OFFS_SATURATION_INQ	0x14
74 #define	DCAM1394_REG_OFFS_GAMMA_INQ		0x18
75 #define	DCAM1394_REG_OFFS_SHUTTER_INQ		0x1C
76 #define	DCAM1394_REG_OFFS_GAIN_INQ		0x20
77 #define	DCAM1394_REG_OFFS_IRIS_INQ		0x24
78 #define	DCAM1394_REG_OFFS_FOCUS_INQ		0x28
79 #define	DCAM1394_REG_OFFS_ZOOM_INQ		0x80
80 #define	DCAM1394_REG_OFFS_PAN_INQ		0x84
81 #define	DCAM1394_REG_OFFS_TILT_INQ		0x88
82 
83 /*
84  * "presence of feature" bit is located in Feature Presence Inquiry
85  * Register(Sec 1.4) Feature Element Inquiry Register(Sec 1.5) and Feature
86  * Status and Control Register(Sec 1.7); driver will use later.
87  */
88 #define	DCAM1394_MASK_READOUT_INQ	0x8000000
89 #define	DCAM1394_SHIFT_READOUT_INQ	27
90 
91 #define	DCAM1394_MASK_ON_OFF_INQ	0x4000000
92 #define	DCAM1394_SHIFT_ON_OFF_INQ	26
93 
94 #define	DCAM1394_MASK_AUTO_INQ		0x2000000
95 #define	DCAM1394_SHIFT_AUTO_INQ		25
96 
97 #define	DCAM1394_MASK_MANUAL_INQ	0x1000000
98 #define	DCAM1394_SHIFT_MANUAL_INQ	24
99 
100 #define	DCAM1394_MASK_MIN_VAL		0xFFF000
101 #define	DCAM1394_SHIFT_MIN_VAL		12
102 
103 #define	DCAM1394_MASK_MAX_VAL		0xFFF
104 #define	DCAM1394_SHIFT_MAX_VAL		0
105 
106 
107 /*
108  * dcam spec: Sec 1.6
109  */
110 #define	DCAM1394_REG_OFFS_CUR_V_FRM_RATE	0x600
111 #define	DCAM1394_SHIFT_CUR_V_FRM_RATE		29
112 
113 #define	DCAM1394_REG_OFFS_CUR_V_MODE		0x604
114 #define	DCAM1394_SHIFT_CUR_V_MODE		29
115 
116 #define	DCAM1394_REG_OFFS_CUR_V_FORMAT		0x608
117 #define	DCAM1394_REG_OFFS_CUR_ISO_CHANNEL	0x60C
118 
119 #define	DCAM1394_REG_OFFS_CAMERA_POWER		0x610
120 #define	  DCAM1394_SHIFT_CAMERA_POWER		31
121 
122 #define	DCAM1394_REG_OFFS_ISO_EN		0x614
123 #define	DCAM1394_REG_OFFS_MEMORY_SAVE		0x618
124 #define	DCAM1394_REG_OFFS_ONE_SHOT		0x61C
125 #define	DCAM1394_REG_OFFS_MEM_SAVE_CH		0x620
126 #define	DCAM1394_REG_OFFS_CUR_MEM_CH		0x624
127 
128 
129 #define	DCAM1394_REG_OFFS_FEATURE_CSR_BASE	0x800
130 
131 #define	DCAM1394_REG_OFFS_BRIGHTNESS_CSR	0x0
132 #define	DCAM1394_REG_OFFS_EXPOSURE_CSR		0x4
133 #define	DCAM1394_REG_OFFS_SHARPNESS_CSR		0x8
134 #define	DCAM1394_REG_OFFS_WHITE_BALANCE_CSR	0xC
135 #define	DCAM1394_REG_OFFS_HUE_CSR		0x10
136 #define	DCAM1394_REG_OFFS_SATURATION_CSR	0x14
137 #define	DCAM1394_REG_OFFS_GAMMA_CSR		0x18
138 #define	DCAM1394_REG_OFFS_SHUTTER_CSR		0x1C
139 #define	DCAM1394_REG_OFFS_GAIN_CSR		0x20
140 #define	DCAM1394_REG_OFFS_IRIS_CSR		0x24
141 #define	DCAM1394_REG_OFFS_FOCUS_CSR		0x28
142 #define	DCAM1394_REG_OFFS_ZOOM_CSR		0x80
143 #define	DCAM1394_REG_OFFS_PAN_CSR		0x84
144 #define	DCAM1394_REG_OFFS_TILT_CSR		0x88
145 
146 #define	DCAM1394_MASK_PRESENCE_INQ		0x80000000
147 #define	DCAM1394_SHIFT_PRESENCE_INQ		31
148 
149 #define	DCAM1394_MASK_ON_OFF			0x2000000
150 #define	DCAM1394_SHIFT_ON_OFF			25
151 
152 #define	DCAM1394_MASK_A_M_MODE			0x1000000
153 #define	DCAM1394_SHIFT_A_M_MODE			24
154 
155 #define	DCAM1394_MASK_VALUE			0xFFF  /* XXX: chk vals */
156 #define	DCAM1394_SHIFT_VALUE			0
157 
158 /*
159  * white balance feature's u and v values
160  */
161 #define	DCAM1394_MASK_U_VALUE			0xFFF000
162 #define	DCAM1394_SHIFT_U_VALUE			12
163 
164 #define	DCAM1394_MASK_V_VALUE			0xFFF
165 #define	DCAM1394_SHIFT_V_VALUE			0
166 
167 int	dcam_reg_read(dcam_state_t *soft_state, dcam1394_reg_io_t *arg);
168 int	dcam_reg_write(dcam_state_t *soft_state, dcam1394_reg_io_t *arg);
169 
170 #ifdef	__cplusplus
171 }
172 #endif
173 
174 #endif	/* _SYS_1394_TARGETS_DCAM1394_REG_H */
175