Home
last modified time | relevance | path

Searched refs:DC1 (Results 1 – 17 of 17) sorted by relevance

/titanic_41/usr/src/lib/libmvec/common/vis/
H A D__vhypot.S38 .word 0x7fe00000, 0 ! DC1
54 #define DC1 %f46 macro
70 ! c0 = vis_fcmple32(DC1,x);
71 ! c2 = vis_fcmple32(DC1,y);
160 ! dnorm = vis_fpsub32(DC1,dmax);
210 ldd [%o3+8],DC1
277 fcmple32 DC1,%f50,%o3 ! (2_0) c0 = vis_fcmple32(DC1,x);
279 fcmple32 DC1,%f34,%o0 ! (2_0) c2 = vis_fcmple32(DC1,y);
313 fcmple32 DC1,%f18,%o3 ! (3_1) c0 = vis_fcmple32(DC1,x);
315 fcmple32 DC1,%f30,%o0 ! (3_1) c2 = vis_fcmple32(DC1,y);
[all …]
H A D__vsqrtf_ultra3.S43 .word 0x3ff00000, 0x00000000 ! DC1 = 0x3ff0000000000000
47 #define DC1 %f4 macro
96 ! db0 = vis_for(db0,DC1);
108 ! res0 += DC1;
139 ldd [%o2+24],DC1
184 for %f60,DC1,%f40 ! (2_0) db0 = vis_for(db0,DC1);
216 for %f58,DC1,%f48 ! (3_1) db0 = vis_for(db0,DC1);
248 for %f54,DC1,%f34 ! (4_1) db0 = vis_for(db0,DC1);
282 for %f32,DC1,%f48 ! (0_0) db0 = vis_for(db0,DC1);
300 faddd %f52,DC1,%f58 ! (2_1) res0 += DC1;
[all …]
H A D__vrsqrt.S45 .word 0x3fe00000, 0x00000000 ! DC1
61 #define DC1 %f54 macro
152 ! res = vis_for(res,DC1);
209 ldd [%o3+0x38],DC1
238 for %f16,DC1,%f44 ! (6_1) res = vis_for(res,DC1);
272 for %f16,DC1,%f28 ! (0_0) res = vis_for(res,DC1);
309 for %f16,DC1,%f44 ! (1_0) res = vis_for(res,DC1);
347 for %f16,DC1,%f28 ! (2_0) res = vis_for(res,DC1);
390 for %f16,DC1,%f44 ! (3_0) res = vis_for(res,DC1);
436 for %f16,DC1,%f24 ! (4_0) res = vis_for(res,DC1);
[all …]
H A D__vhypotf.S40 .word 0x3ff00000, 0x00000000 ! DC1 = 0x3ff0000000000000
48 #define DC1 %f10 macro
124 ! h0 = vis_for(h0,DC1);
143 ! res0 += DC1;
178 ldd [%o3+24],DC1
297 for %f60,DC1,%f46 ! (3_1) h0 = vis_for(h0,DC1);
334 for %f60,DC1,%f46 ! (4_1) h0 = vis_for(h0,DC1);
379 for %f60,DC1,%f46 ! (0_0) h0 = vis_for(h0,DC1);
414 faddd %f40,DC1,%f40 ! (3_1) res0 += DC1;
425 for %f60,DC1,%f46 ! (1_0) h0 = vis_for(h0,DC1);
[all …]
H A D__vrhypotf.S172 .word 0x3ff00000, 0 ! DC1
198 #define DC1 %f8 macro
264 ! hyp0 = vis_for(hyp0,DC1);
310 ldd [TBL+TBL_SHIFT+8],DC1
429 for %f30,DC1,%f28 ! (3_1) hyp0 = vis_for(hyp0,DC1);
468 for %f30,DC1,%f28 ! (4_1) hyp0 = vis_for(hyp0,DC1);
510 for %f30,DC1,%f28 ! (0_0) hyp0 = vis_for(hyp0,DC1);
556 for %f30,DC1,%f28 ! (1_0) hyp0 = vis_for(hyp0,DC1);
617 for %f30,DC1,%f28 ! (2_1) hyp0 = vis_for(hyp0,DC1);
672 for %f30,DC1,%f28 ! (3_1) hyp0 = vis_for(hyp0,DC1);
[all …]
H A D__vatanf.S40 .word 0x00020000, 0x00000000 ! DC1
171 #define DC1 %f60 macro
219 ! y = vis_fpadd32(x,DC1);
274 ldd [%l2+24],DC1
324 fpadd32 %f22,DC1,%f24 ! (0_0) y = vis_fpadd32(x,dconst1);
347 fpadd32 %f20,DC1,%f24 ! (1_0) y = vis_fpadd32(x,dconst1);
371 fpadd32 %f18,DC1,%f24 ! (2_0) y = vis_fpadd32(x,dconst1);
406 fpadd32 %f16,DC1,%f24 ! (3_0) y = vis_fpadd32(x,dconst1);
444 fpadd32 %f14,DC1,%f24 ! (4_0) y = vis_fpadd32(x,dconst1);
485 fpadd32 %f36,DC1,%f24 ! (5_0) y = vis_fpadd32(x,dconst1);
[all …]
/titanic_41/usr/src/uts/sun4u/sys/
H A Dopl.h84 DC1, enumerator
/titanic_41/usr/src/uts/sun4u/opl/os/
H A Dopl.c84 { "DC1", OPL_MAX_BOARDS_DC1, DC1, STD_DISPATCH_TABLE },
921 case DC1: in plat_get_cpu_unum()
/titanic_41/usr/src/cmd/localedef/data/
H A Dwidths.txt4756 <CJK_UNIFIED_IDEOGRAPH-3DC1> 2
12938 <CJK_UNIFIED_IDEOGRAPH-5DC1> 2
17034 <CJK_UNIFIED_IDEOGRAPH-6DC1> 2
21130 <CJK_UNIFIED_IDEOGRAPH-7DC1> 2
25226 <CJK_UNIFIED_IDEOGRAPH-8DC1> 2
29322 <CJK_UNIFIED_IDEOGRAPH-9DC1> 2
H A Dzh_CN.UTF-8.src74987 <CJK_UNIFIED_IDEOGRAPH-8DC1> <X7C4A>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-8DC…
86185 <CJK_UNIFIED_IDEOGRAPH-5DC1> <XA7DB>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-5DC…
90857 <CJK_UNIFIED_IDEOGRAPH-6DC1> <XB9A5>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-6DC…
90868 <CJK_UNIFIED_IDEOGRAPH-7DC1> <XB9B0>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-7DC…
98643 <CJK_UNIFIED_IDEOGRAPH-9DC1> <XD8AC>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-9DC…
H A Dzh_SG.UTF-8.src74987 <CJK_UNIFIED_IDEOGRAPH-8DC1> <X7C4A>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-8DC…
86185 <CJK_UNIFIED_IDEOGRAPH-5DC1> <XA7DB>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-5DC…
90857 <CJK_UNIFIED_IDEOGRAPH-6DC1> <XB9A5>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-6DC…
90868 <CJK_UNIFIED_IDEOGRAPH-7DC1> <XB9B0>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-7DC…
98643 <CJK_UNIFIED_IDEOGRAPH-9DC1> <XD8AC>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-9DC…
H A DGB18030.cm13573 <CJK_UNIFIED_IDEOGRAPH-3DC1> \x82\x31\xEB\…
21755 <CJK_UNIFIED_IDEOGRAPH-5DC1> \x8E\x5F
25851 <CJK_UNIFIED_IDEOGRAPH-6DC1> \x9B\xF9
29947 <CJK_UNIFIED_IDEOGRAPH-7DC1> \xBE\x66
34043 <CJK_UNIFIED_IDEOGRAPH-8DC1> \xDA\x95
38139 <CJK_UNIFIED_IDEOGRAPH-9DC1> \xFA\x5E
H A DUTF-8.cm14174 <CJK_UNIFIED_IDEOGRAPH-3DC1> \xE3\xB7\x81
22356 <CJK_UNIFIED_IDEOGRAPH-5DC1> \xE5\xB7\x81
26452 <CJK_UNIFIED_IDEOGRAPH-6DC1> \xE6\xB7\x81
30548 <CJK_UNIFIED_IDEOGRAPH-7DC1> \xE7\xB7\x81
34644 <CJK_UNIFIED_IDEOGRAPH-8DC1> \xE8\xB7\x81
38740 <CJK_UNIFIED_IDEOGRAPH-9DC1> \xE9\xB7\x81
H A Dja_JP.UTF-8.src67564 <CJK_UNIFIED_IDEOGRAPH-9DC1> <XDEB1>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-9DC1>
H A Dko_KR.UTF-8.src49047 …CJK_UNIFIED_IDEOGRAPH-9DC1> "<X7820><X785C><X7861>";"<XCA><X05><X05>";"<X05><X05><X0…
/titanic_41/usr/src/cmd/terminfo/
H A Dtermcap.src9424 # No delays specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
9441 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
9614 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
10132 # require/do not require receipt of a DC1 from host after each LF*
10642 # "stty ixon -ixany" to enable DC3/DC1 flow control!
14412 # Delays not specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
14492 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
14534 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
14920 # The modem interface is permitted to discard LF (maybe DC1), otherwise
14938 # Enable DC3/DC1 flow control with "stty ixon -ixany".
[all …]
H A Dterminfo.src10640 # No delays specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
10659 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
10892 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
11468 # require/do not require receipt of a DC1 from host after each LF*
12031 # "stty ixon -ixany" to enable DC3/DC1 flow control!
16275 # Delays not specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
16363 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
16408 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
16836 # The modem interface is permitted to discard LF (maybe DC1), otherwise
16857 # Enable DC3/DC1 flow control with "stty ixon -ixany".
[all …]