Home
last modified time | relevance | path

Searched refs:DBG_MSIQ (Results 1 – 4 of 4) sorted by relevance

/titanic_41/usr/src/uts/sun4/io/px/
H A Dpx_msiq.c55 DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_attach\n"); in px_msiq_attach()
110 DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_detach\n"); in px_msiq_detach()
113 DBG(DBG_MSIQ, px_p->px_dip, in px_msiq_detach()
155 DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_alloc\n"); in px_msiq_alloc()
180 DBG(DBG_MSIQ, px_p->px_dip, in px_msiq_alloc()
215 DBG(DBG_MSIQ, px_p->px_dip, in px_msiq_alloc()
236 DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_alloc_based_on_cpuid: " in px_msiq_alloc_based_on_cpuid()
269 DBG(DBG_MSIQ, px_p->px_dip, in px_msiq_alloc_based_on_cpuid()
289 DBG(DBG_MSIQ, px_p->px_dip, in px_msiq_alloc_based_on_cpuid()
304 DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_free: msiq_id 0x%x", msiq_id); in px_msiq_free()
[all …]
H A Dpx_msi.c58 DBG(DBG_MSIQ, dip, "px_msi_attach\n"); in px_msi_attach()
91 DBG(DBG_MSIQ, dip, "ndi_irm_create() failed\n"); in px_msi_attach()
110 DBG(DBG_MSIQ, dip, "px_msi_detach\n"); in px_msi_detach()
332 DBG(DBG_MSIQ, dip, "px_msi_get_props\n"); in px_msi_get_props()
338 DBG(DBG_MSIQ, dip, "#msi=%d\n", msi_state_p->msi_cnt); in px_msi_get_props()
351 DBG(DBG_MSIQ, dip, "msi_1st_msinum=%d\n", msi_state_p->msi_1st_msinum); in px_msi_get_props()
357 DBG(DBG_MSIQ, dip, "msi-data-mask=0x%x\n", in px_msi_get_props()
364 DBG(DBG_MSIQ, dip, "msix-data-width=%d\n", in px_msi_get_props()
396 DBG(DBG_MSIQ, dip, "msi_addr32=0x%llx\n", msi_state_p->msi_addr32); in px_msi_get_props()
397 DBG(DBG_MSIQ, dip, "msi_addr64=0x%llx\n", msi_state_p->msi_addr64); in px_msi_get_props()
H A Dpx_debug.h47 /* 8 */ DBG_MSIQ, enumerator
H A Dpx_intr.c1168 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: rdip=%s%d handler=0x%x " in px_add_msiq_intr()
1183 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " in px_add_msiq_intr()
1200 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " in px_add_msiq_intr()
1226 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: pil=0x%x mondo=0x%x\n", in px_add_msiq_intr()
1273 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: done! Interrupt 0x%x pil=%x\n", in px_add_msiq_intr()
1288 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: Failed! Interrupt 0x%x pil=%x\n", in px_add_msiq_intr()
1313 DBG(DBG_MSIQ, dip, "px_rem_msiq_intr: rdip=%s%d msiq_id=%x ino=%x\n", in px_rem_msiq_intr()