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Searched refs:CRA (Results 1 – 3 of 3) sorted by relevance

/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dvsc7326_reg.h39 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1)) macro
42 #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
43 #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
44 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
45 #define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */
46 #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
47 #define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
48 #define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
49 #define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
50 #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
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H A Dvsc7321_reg.h39 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1)) macro
42 #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
43 #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
44 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
45 #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
46 #define REG_CRC_CNT CRA(0x7,0xf,0x0a) /* CRC error count */
47 #define REG_CRC_CFG CRA(0x7,0xf,0x0b) /* CRC config */
48 #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
49 #define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */
50 #define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */
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H A Dvsc7326.c589 vsc_write(mac->adapter, CRA(4, port, i), 0); in mac_disable()