Searched refs:C1DRB3 (Results 1 – 2 of 2) sorted by relevance
| /titanic_41/usr/src/uts/intel/io/drm/ | ||
| H A D | i915_gem_tiling.c | 172 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { in i915_gem_detect_bit_6_swizzle() |
| H A D | i915_drv.h | 1040 #define C1DRB3 0x10606 macro |