1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright 2014 QLogic Corporation 22 * The contents of this file are subject to the terms of the 23 * QLogic End User License (the "License"). 24 * You may not use this file except in compliance with the License. 25 * 26 * You can obtain a copy of the License at 27 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/ 28 * QLogic_End_User_Software_License.txt 29 * See the License for the specific language governing permissions 30 * and limitations under the License. 31 * 32 */ 33 34 /* Init operation types and structures */ 35 enum { 36 OP_RD = 0x1, /* read a single register */ 37 OP_WR, /* write a single register */ 38 OP_SW, /* copy a string to the device */ 39 OP_ZR, /* clear memory */ 40 OP_ZP, /* unzip then copy with DMAE */ 41 OP_WR_64, /* write 64 bit pattern */ 42 OP_WB, /* copy a string using DMAE */ 43 #ifndef FW_ZIP_SUPPORT /* ! BNX2X_UPSTREAM */ 44 OP_FW, /* copy an array from fw data (only used with unzipped FW) */ 45 #endif 46 OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */ 47 OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */ 48 OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */ 49 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 50 OP_IF_PHASE, 51 OP_RT, 52 OP_DELAY, 53 OP_VERIFY, 54 #endif 55 OP_MAX 56 }; 57 58 enum { 59 STAGE_START, 60 STAGE_END, 61 }; 62 63 /* Returns the index of start or end of a specific block stage in ops array*/ 64 #define BLOCK_OPS_IDX(block, stage, end) \ 65 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end)) 66 67 68 /* structs for the various opcodes */ 69 struct raw_op { 70 u32 op:8; 71 u32 offset:24; 72 u32 raw_data; 73 }; 74 75 struct op_read { 76 u32 op:8; 77 u32 offset:24; 78 u32 val; 79 }; 80 81 struct op_write { 82 u32 op:8; 83 u32 offset:24; 84 u32 val; 85 }; 86 87 struct op_arr_write { 88 u32 op:8; 89 u32 offset:24; 90 #ifdef __BIG_ENDIAN 91 u16 data_len; 92 u16 data_off; 93 #else /* __LITTLE_ENDIAN */ 94 u16 data_off; 95 u16 data_len; 96 #endif 97 }; 98 99 struct op_zero { 100 u32 op:8; 101 u32 offset:24; 102 u32 len; 103 }; 104 105 struct op_if_mode { 106 u32 op:8; 107 u32 cmd_offset:24; 108 u32 mode_bit_map; 109 }; 110 111 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 112 struct op_if_phase { 113 u32 op:8; 114 u32 cmd_offset:24; 115 u32 phase_bit_map; 116 }; 117 118 struct op_delay { 119 u32 op:8; 120 u32 reserved:24; 121 u32 delay; 122 }; 123 #endif 124 125 union init_op { 126 struct op_read read; 127 struct op_write write; 128 struct op_arr_write arr_wr; 129 struct op_zero zero; 130 struct raw_op raw; 131 struct op_if_mode if_mode; 132 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 133 struct op_if_phase if_phase; 134 struct op_delay delay; 135 #endif 136 }; 137 138 139 /* Init Phases */ 140 enum { 141 PHASE_COMMON, 142 PHASE_PORT0, 143 PHASE_PORT1, 144 PHASE_PF0, 145 PHASE_PF1, 146 PHASE_PF2, 147 PHASE_PF3, 148 PHASE_PF4, 149 PHASE_PF5, 150 PHASE_PF6, 151 PHASE_PF7, 152 NUM_OF_INIT_PHASES 153 }; 154 155 /* Init Modes */ 156 enum { 157 MODE_ASIC = 0x00000001, 158 MODE_FPGA = 0x00000002, 159 MODE_EMUL = 0x00000004, 160 MODE_E2 = 0x00000008, 161 MODE_E3 = 0x00000010, 162 MODE_PORT2 = 0x00000020, 163 MODE_PORT4 = 0x00000040, 164 MODE_SF = 0x00000080, 165 MODE_MF = 0x00000100, 166 MODE_MF_SD = 0x00000200, 167 MODE_MF_SI = 0x00000400, 168 MODE_MF_AFEX = 0x00000800, 169 MODE_E3_A0 = 0x00001000, 170 MODE_E3_B0 = 0x00002000, 171 MODE_COS3 = 0x00004000, 172 MODE_COS6 = 0x00008000, 173 MODE_LITTLE_ENDIAN = 0x00010000, 174 MODE_BIG_ENDIAN = 0x00020000, 175 }; 176 177 /* Init Blocks */ 178 enum { 179 BLOCK_ATC, 180 BLOCK_BRB1, 181 BLOCK_CCM, 182 BLOCK_CDU, 183 BLOCK_CFC, 184 BLOCK_CSDM, 185 BLOCK_CSEM, 186 BLOCK_DBG, 187 BLOCK_DMAE, 188 BLOCK_DORQ, 189 BLOCK_HC, 190 BLOCK_IGU, 191 BLOCK_MISC, 192 BLOCK_NIG, 193 BLOCK_PBF, 194 BLOCK_PGLUE_B, 195 BLOCK_PRS, 196 BLOCK_PXP2, 197 BLOCK_PXP, 198 BLOCK_QM, 199 BLOCK_SRC, 200 BLOCK_TCM, 201 BLOCK_TM, 202 BLOCK_TSDM, 203 BLOCK_TSEM, 204 BLOCK_UCM, 205 BLOCK_UPB, 206 BLOCK_USDM, 207 BLOCK_USEM, 208 BLOCK_XCM, 209 BLOCK_XPB, 210 BLOCK_XSDM, 211 BLOCK_XSEM, 212 BLOCK_MISC_AEU, 213 NUM_OF_INIT_BLOCKS 214 }; 215 216