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Searched refs:B0_HWE_IMSK (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/common/io/yge/
H A Dyge.c816 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); in yge_reset()
817 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_reset()
1425 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); in yge_detach()
1426 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_detach()
1729 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); in yge_suspend()
1730 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_suspend()
1782 CSR_WRITE_4(dev, B0_HWE_IMSK, in yge_resume()
2152 CSR_WRITE_4(dev, B0_HWE_IMSK, in yge_intr_hwerr()
2154 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_intr_hwerr()
2614 CSR_WRITE_4(dev, B0_HWE_IMSK, dev->d_intrhwemask); in yge_start_port()
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H A Dyge.h262 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ macro