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Searched refs:AcpiHwWrite (Results 1 – 6 of 6) sorted by relevance

/titanic_41/usr/src/uts/intel/io/acpica/hardware/
H A Dhwregs.c235 AcpiHwWrite ( in AcpiHwWrite() function
386 Status = AcpiHwWrite (Pm1aControl, &AcpiGbl_FADT.XPm1aControlBlock); in AcpiHwWritePm1Control()
394 Status = AcpiHwWrite (Pm1bControl, &AcpiGbl_FADT.XPm1bControlBlock); in AcpiHwWritePm1Control()
591 Status = AcpiHwWrite (Value, &AcpiGbl_FADT.XPm2ControlBlock); in AcpiHwRegisterWrite()
596 Status = AcpiHwWrite (Value, &AcpiGbl_FADT.XPmTimerBlock); in AcpiHwRegisterWrite()
703 Status = AcpiHwWrite (Value, RegisterA); in AcpiHwWriteMultiple()
723 Status = AcpiHwWrite (Value, RegisterB); in AcpiHwWriteMultiple()
H A Dhwgpe.c169 Status = AcpiHwWrite (EnableMask, &GpeRegisterInfo->EnableAddress); in AcpiHwLowSetGpe()
211 Status = AcpiHwWrite (RegisterBit, &GpeRegisterInfo->StatusAddress); in AcpiHwClearGpe()
335 Status = AcpiHwWrite (EnableMask, &GpeRegisterInfo->EnableAddress); in AcpiHwGpeEnableWrite()
409 Status = AcpiHwWrite (0xFF, &GpeBlock->RegisterInfo[i].StatusAddress); in AcpiHwClearGpeBlock()
H A Dhwxface.c109 Status = AcpiHwWrite (AcpiGbl_FADT.ResetValue, ResetReg); in AcpiReset()
/titanic_41/usr/src/uts/intel/io/acpica/events/
H A Devgpeblk.c313 Status = AcpiHwWrite (0x00, &ThisRegister->EnableAddress); in AcpiEvCreateGpeInfoBlocks()
321 Status = AcpiHwWrite (0xFF, &ThisRegister->StatusAddress); in AcpiEvCreateGpeInfoBlocks()
/titanic_41/usr/src/uts/intel/sys/acpi/
H A Dachware.h84 AcpiHwWrite (
/titanic_41/usr/src/uts/intel/io/acpica/
H A Dchanges.txt10 AcpiHwRead/AcpiHwWrite for the Generic Address Structure. There have been
40 support in AcpiHwRead/AcpiHwWrite. Problem could cause incorrect behavior