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Searched refs:A_PL_CAUSE (Results 1 – 12 of 12) sorted by relevance

/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dch_subr.c226 u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE); in fpga_slow_intr()
259 t1_write_reg_4(adapter, A_PL_CAUSE, cause); in fpga_slow_intr()
1090 u32 pl_intr = t1_read_reg_4(adapter, A_PL_CAUSE); in t1_interrupts_clear()
1092 t1_write_reg_4(adapter, A_PL_CAUSE, in t1_interrupts_clear()
1106 u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE); in asic_slow_intr()
1133 t1_write_reg_4(adapter, A_PL_CAUSE, cause); in asic_slow_intr()
1134 (void) t1_read_reg_4(adapter, A_PL_CAUSE); /* flush writes */ in asic_slow_intr()
H A Dmc3.c98 t1_write_reg_4(mc3->adapter, A_PL_CAUSE, F_PL_INTR_MC3); in t1_mc3_intr_clear()
103 t1_write_reg_4(mc3->adapter, A_PL_CAUSE, in t1_mc3_intr_clear()
H A Dulp.c58 t1_write_reg_4(ulp->adapter, A_PL_CAUSE, F_PL_INTR_ULP); in t1_ulp_intr_clear()
H A Dtp.c363 t1_write_reg_4(tp->adapter, A_PL_CAUSE, FPGA_PCIX_INTERRUPT_TP); in t1_tp_intr_clear()
368 t1_write_reg_4(tp->adapter, A_PL_CAUSE, F_PL_INTR_TP); in t1_tp_intr_clear()
H A Dmc4.c242 t1_write_reg_4(mc4->adapter, A_PL_CAUSE, F_PL_INTR_MC4); in t1_mc4_intr_clear()
H A Dpm3393.c249 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE); in pm3393_interrupt_clear()
251 t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr); in pm3393_interrupt_clear()
H A Dch_mac.c144 t1_write_reg_4(mac->adapter, A_PL_CAUSE, in mac_intr_clear()
H A Despi.c147 t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI); in t1_espi_intr_clear()
H A Dmc5.c554 t1_write_reg_4(mc5->adapter, A_PL_CAUSE, F_PL_INTR_MC5); in t1_mc5_intr_clear()
H A Dregs.h1779 #define A_PL_CAUSE 0xa04 macro
/titanic_41/usr/src/uts/common/io/chxge/
H A Dsge.c540 t1_write_reg_4(sge->obj, A_PL_CAUSE, SGE_PL_INTR_MASK); in t1_sge_intr_clear()
605 t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_SGE_DATA); in sge_data_in()
H A Dpe.c1519 t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_EXT); in ext_intr_task()