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Searched refs:AR_PHY_TIMING_CTRL4 (Results 1 – 4 of 4) sorted by relevance

/titanic_41/usr/src/uts/common/io/arn/
H A Darn_calib.c215 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ath9k_hw_setup_calibration()
244 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ath9k_hw_setup_calibration()
281 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ath9k_hw_per_calibration()
469 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ath9k_hw_iqcalibrate()
472 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ath9k_hw_iqcalibrate()
482 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ath9k_hw_iqcalibrate()
H A Darn_phy.h196 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) macro
H A Darn_eeprom.c2230 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_eeprom_set_def_board_values()
2231 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & in ath9k_hw_eeprom_set_def_board_values()
2454 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_eeprom_set_4k_board_values()
2455 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & in ath9k_hw_eeprom_set_4k_board_values()
H A Darn_hw.c2012 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ath9k_hw_9280_spur_mitigate()
2018 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ath9k_hw_9280_spur_mitigate()
2236 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ath9k_hw_spur_mitigate()
2242 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ath9k_hw_spur_mitigate()