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Searched refs:zl3073x_write_u8 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/dpll/zl3073x/
H A Dcore.c178 int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val) in zl3073x_write_u8() function
352 rc = zl3073x_write_u8(zldev, op_reg, op_val); in zl3073x_mb_op()
375 rc = zl3073x_write_u8(zldev, ZL_REG_HWREG_OP, op | ZL_HWREG_OP_PENDING); in zl3073x_do_hwreg_op()
618 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_IDX, channel); in zl3073x_ref_phase_offsets_update()
624 rc = zl3073x_write_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST, in zl3073x_ref_phase_offsets_update()
656 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_3_0, in zl3073x_ref_freq_meas_latch()
660 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_4, in zl3073x_ref_freq_meas_latch()
666 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL, type); in zl3073x_ref_freq_meas_latch()
809 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl); in zl3073x_dev_phase_avg_factor_set()
849 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl); in zl3073x_dev_phase_meas_setup()
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H A Dref.c222 rc = zl3073x_write_u8(zldev, ZL_REG_REF_SYNC_CTRL, in zl3073x_ref_state_set()
H A Dcore.h133 int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val);
H A Ddpll.c1887 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); in zl3073x_dpll_init_fine_phase_adjust()
1891 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); in zl3073x_dpll_init_fine_phase_adjust()
1899 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); in zl3073x_dpll_init_fine_phase_adjust()