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Searched refs:zl3073x_write_u8 (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/dpll/zl3073x/
H A Dchan.c51 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_DF_READ(index), in zl3073x_chan_state_update()
99 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(index), in zl3073x_chan_nco_mode_set()
121 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_DF_READ(index), df_read); in zl3073x_chan_nco_mode_set()
132 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(index), in zl3073x_chan_nco_mode_set()
297 return zl3073x_write_u8(zldev, ZL_REG_DPLL_TOD_CTRL(ch), in zl3073x_chan_tod_ctrl()
495 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_TIE_CTRL_MASK, BIT(ch)); in zl3073x_chan_tie_write()
499 return zl3073x_write_u8(zldev, ZL_REG_DPLL_TIE_CTRL, in zl3073x_chan_tie_write()
541 rc = zl3073x_write_u8(zldev, ZL_REG_OUTPUT_PHASE_STEP_NUMBER, 1); in zl3073x_chan_phase_step()
551 return zl3073x_write_u8(zldev, ZL_REG_OUTPUT_PHASE_STEP_CTRL, ctrl); in zl3073x_chan_phase_step()
579 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_CTRL(index), in zl3073x_chan_state_set()
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H A Dcore.c179 int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val) in zl3073x_write_u8() function
353 rc = zl3073x_write_u8(zldev, op_reg, op_val); in zl3073x_mb_op()
377 rc = zl3073x_write_u8(zldev, ZL_REG_HWREG_OP, op | ZL_HWREG_OP_PENDING); in zl3073x_do_hwreg_op()
614 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_IDX, channel); in zl3073x_ref_phase_offsets_update()
620 rc = zl3073x_write_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST, in zl3073x_ref_phase_offsets_update()
654 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_3_0, in zl3073x_ref_freq_meas_latch()
658 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_4, in zl3073x_ref_freq_meas_latch()
664 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL, type); in zl3073x_ref_freq_meas_latch()
757 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl); in zl3073x_dev_phase_avg_factor_set()
797 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl); in zl3073x_dev_phase_meas_setup()
[all …]
H A Dout.c151 rc = zl3073x_write_u8(zldev, ZL_REG_OUTPUT_MODE, out->mode); in zl3073x_out_state_set()
H A Dref.c222 rc = zl3073x_write_u8(zldev, ZL_REG_REF_SYNC_CTRL, in zl3073x_ref_state_set()
H A Dcore.h153 int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val);
H A Ddpll.c2303 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); in zl3073x_dpll_init_fine_phase_adjust()
2307 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); in zl3073x_dpll_init_fine_phase_adjust()
2315 return zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); in zl3073x_dpll_init_fine_phase_adjust()