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Searched refs:xcc_mask (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_2.c45 uint32_t xcc_mask) in gfxhub_v1_2_xcc_setup_vm_pt_regs() argument
50 for_each_inst(i, xcc_mask) { in gfxhub_v1_2_xcc_setup_vm_pt_regs()
68 uint32_t xcc_mask; in gfxhub_v1_2_setup_vm_pt_regs() local
70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_setup_vm_pt_regs()
71 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, xcc_mask); in gfxhub_v1_2_setup_vm_pt_regs()
75 uint32_t xcc_mask) in gfxhub_v1_2_xcc_init_gart_aperture_regs() argument
87 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
92 for_each_inst(i, xcc_mask) { in gfxhub_v1_2_xcc_init_gart_aperture_regs()
127 uint32_t xcc_mask) in gfxhub_v1_2_xcc_init_system_aperture_regs() argument
133 for_each_inst(i, xcc_mask) { in gfxhub_v1_2_xcc_init_system_aperture_regs()
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H A Dgfxhub_v12_1.c63 uint32_t xcc_mask) in gfxhub_v12_1_xcc_setup_vm_pt_regs() argument
68 for_each_inst(i, xcc_mask) { in gfxhub_v12_1_xcc_setup_vm_pt_regs()
86 uint32_t xcc_mask; in gfxhub_v12_1_setup_vm_pt_regs() local
88 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v12_1_setup_vm_pt_regs()
90 xcc_mask); in gfxhub_v12_1_setup_vm_pt_regs()
94 uint32_t xcc_mask) in gfxhub_v12_1_xcc_init_gart_aperture_regs() argument
104 gfxhub_v12_1_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
109 for_each_inst(i, xcc_mask) { in gfxhub_v12_1_xcc_init_gart_aperture_regs()
143 uint32_t xcc_mask) in gfxhub_v12_1_xcc_init_system_aperture_regs() argument
154 for_each_inst(i, xcc_mask) { in gfxhub_v12_1_xcc_init_system_aperture_regs()
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H A Dgfx_v12_1.c349 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_set_kiq_pm4_funcs()
653 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_init_rlcg_reg_access_ctrl()
697 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_rlc_init()
721 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_mec_init()
862 for (logic_xcc = 0; logic_xcc < NUM_XCC(adev->gfx.xcc_mask); logic_xcc++) { in gfx_v12_1_ih_to_xcc_inst()
1068 ((1 << (i / 2)) & adev->gfx.xcc_mask)) { in gfx_v12_1_rlc_backdoor_autoload_copy_ucode()
1243 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_rlc_backdoor_autoload_enable()
1279 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_alloc_ip_dump()
1315 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_ip_print()
1374 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_ip_dump()
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H A Dgfx_v9_4_3.c341 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
350 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
626 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_mec_init()
804 NUM_XCC(adev->gfx.xcc_mask) / in gfx_v9_4_3_switch_compute_partition()
809 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_switch_compute_partition()
831 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); in gfx_v9_4_3_ih_to_xcc_inst()
947 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_alloc_ip_dump()
999 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_init()
1126 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_fini()
1282 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_constants_init()
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H A Dcyan_skillfish_reg_init.c36 adev->gfx.xcc_mask = 1; in cyan_skillfish_reg_base_init()
H A Damdgpu_gfx.c215 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_compute_queue_acquire()
539 int xcc_inst = ffs(adev->gfx.xcc_mask) - 1; in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
548 num_xcc = hweight16(adev->gfx.xcc_mask); in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
1211 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_ras_error_func()
1212 uint32_t xcc_mask = GENMASK(num_xcc - 1, 0); in amdgpu_gfx_ras_error_func() local
1220 for_each_inst(i, xcc_mask) in amdgpu_gfx_ras_error_func()
1652 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_set_compute_partition()
1816 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_run_cleaner_shader()
H A Damdgpu_discovery.c923 adev->gfx.xcc_mask &= ~BIT(inst); in amdgpu_discovery_read_from_harvest_table()
1213 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1760 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1860 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
3100 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
3129 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
3159 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
3206 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
3237 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
3272 adev->gfx.xcc_mask in amdgpu_discovery_set_ip_blocks()
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H A Damdgpu_mes.c108 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_mes_init()
289 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_mes_fini()
H A Damdgpu_gmc.c1633 uint32_t xcc_mask; in amdgpu_gmc_init_acpi_mem_ranges()
1635 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gmc_init_acpi_mem_ranges()
1636 xcc_mask = (1U << num_xcc) - 1; in amdgpu_gmc_init_acpi_mem_ranges() local
1638 for_each_inst(xcc_id, xcc_mask) { in amdgpu_gmc_init_acpi_mem_ranges()
H A Damdgpu_virt.c1444 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_vfi_reg_rw()
1566 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
H A Dmes_v12_1.c1607 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_sw_init()
1654 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_sw_fini()
1847 u32 num_xcc_per_xcp, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_setup_coop_mode()
1957 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_hw_init()
H A Damdgpu_vm.h528 uint32_t xcc_mask);
H A Dnbio_v7_9.c439 0xff & ~(adev->gfx.xcc_mask)); in nbio_v7_9_init_registers()
H A Dsdma_v4_4_2.c145 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
150 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
H A Damdgpu_vm.c1720 uint32_t xcc_mask) in amdgpu_vm_flush_compute_tlb() argument
1740 for_each_inst(xcc, xcc_mask) { in amdgpu_vm_flush_compute_tlb()
H A Dsdma_v7_1.c1303 for (xcc_id = 0; xcc_id < fls(adev->gfx.xcc_mask); xcc_id++) { in sdma_v7_1_sw_init()
H A Damdgpu_psp.c2456 ras_cmd->ras_in_message.init_flags.xcc_mask = in psp_ras_initialize()
2457 adev->gfx.xcc_mask; in psp_ras_initialize()
H A Dgfx_v8_0.c5174 adev->gfx.xcc_mask = 1; in gfx_v8_0_early_init()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c149 NUM_XCC(node->xcc_mask), in allocate_mqd()
409 if (check_mul_overflow(per_xcc_size, NUM_XCC(mm->dev->xcc_mask), ctl_stack_size)) in get_checkpoint_info()
442 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in checkpoint_mqd_v9_4_3()
627 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in init_mqd_hiq_v9_4_3()
654 uint32_t xcc_mask = mm->dev->xcc_mask; in hiq_load_mqd_kiq_v9_4_3() local
659 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
678 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_hiq_mqd_v9_4_3() local
684 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
704 uint32_t xcc_mask = mm->dev->xcc_mask; in check_preemption_failed_v9_4_3() local
709 for_each_inst(xcc_id, xcc_mask) { in check_preemption_failed_v9_4_3()
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H A Dkfd_mqd_manager_v12_1.c59 int inc = NUM_XCC(mm->dev->xcc_mask); in mqd_symmetrically_map_cu_mask_v12_1()
60 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; in mqd_symmetrically_map_cu_mask_v12_1()
148 mqd_size *= NUM_XCC(node->xcc_mask); in allocate_mqd()
464 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in init_mqd_v12_1()
491 NUM_XCC(mm->dev->xcc_mask); in init_mqd_v12_1()
514 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in update_mqd_v12_1()
535 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_mqd_v12_1() local
544 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v12_1()
565 uint32_t xcc_mask = mm->dev->xcc_mask; in load_mqd_v12_1() local
570 for_each_inst(xcc_id, xcc_mask) { in load_mqd_v12_1()
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H A Dkfd_device_queue_manager.c155 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_sh_mem_settings() local
158 for_each_inst(xcc_id, xcc_mask) in program_sh_mem_settings()
268 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in add_queue_mes()
307 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in remove_queue_mes_on_reset_option()
428 ffs(dqm->dev->xcc_mask) - 1); in reset_queue_mes()
431 ffs(dqm->dev->xcc_mask) - 1); in reset_queue_mes()
480 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in reset_queues_mes()
656 uint32_t xcc_mask = dqm->dev->xcc_mask; in allocate_vmid()
636 uint32_t xcc_mask = dqm->dev->xcc_mask; program_trap_handler_settings() local
917 uint32_t xcc_mask = dev->xcc_mask; dbgdev_wave_reset_wavefronts() local
1709 uint32_t xcc_mask = dqm->dev->xcc_mask; set_pasid_vmid_mapping() local
1724 uint32_t xcc_mask = dqm->dev->xcc_mask; init_interrupts() local
3966 uint32_t xcc_mask = dqm->dev->xcc_mask; dqm_debugfs_hqds() local
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H A Dkfd_device.c697 uint32_t xcc_mask = node->xcc_mask; in kfd_setup_interrupt_bitmap() local
723 for_each_inst(xcc, xcc_mask) { in kfd_setup_interrupt_bitmap()
732 for_each_inst(xcc, xcc_mask) { in kfd_setup_interrupt_bitmap()
896 &node->xcc_mask); in kgd2kfd_device_init()
899 node->xcc_mask = in kgd2kfd_device_init()
900 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; in kgd2kfd_device_init()
H A Dkfd_process_queue_manager.c98 ffs(pdd->dev->xcc_mask) - 1); in kfd_process_dequeue_from_device()
1079 set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->xcc_mask)); in kfd_criu_restore_queue()
1161 num_xccs = NUM_XCC(q->device->xcc_mask); in pqm_debugfs_mqds()
H A Dkfd_process.c322 &max_waves_per_cu, ffs(dev->xcc_mask) - 1); in kfd_get_cu_occupancy()
332 wave_cnt += (NUM_XCC(dev->xcc_mask) * in kfd_get_cu_occupancy()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_8_ppt.c1746 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { in smu_v15_0_8_get_gpu_metrics()
1761 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { in smu_v15_0_8_get_gpu_metrics()
1822 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { in smu_v15_0_8_get_gpu_metrics()

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