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Searched refs:xcc_mask (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c162 NUM_XCC(node->xcc_mask), in allocate_mqd()
399 if (check_mul_overflow(m->cp_hqd_cntl_stack_size, NUM_XCC(mm->dev->xcc_mask), ctl_stack_size)) in get_checkpoint_info()
426 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in checkpoint_mqd_v9_4_3()
597 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in init_mqd_hiq_v9_4_3()
624 uint32_t xcc_mask = mm->dev->xcc_mask; in hiq_load_mqd_kiq_v9_4_3() local
629 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
648 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_hiq_mqd_v9_4_3() local
654 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
674 uint32_t xcc_mask = mm->dev->xcc_mask; in check_preemption_failed_v9_4_3() local
679 for_each_inst(xcc_id, xcc_mask) { in check_preemption_failed_v9_4_3()
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H A Dkfd_mqd_manager.c82 NUM_XCC(dev->xcc_mask); in allocate_sdma_mqd()
111 int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask); in mqd_symmetrically_map_cu_mask()
112 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; in mqd_symmetrically_map_cu_mask()
H A Dkfd_device_queue_manager.c149 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_sh_mem_settings() local
152 for_each_inst(xcc_id, xcc_mask) in program_sh_mem_settings()
260 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in add_queue_mes()
291 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in remove_queue_mes()
523 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_trap_handler_settings() local
527 for_each_inst(xcc_id, xcc_mask) in program_trap_handler_settings()
797 uint32_t xcc_mask = dev->xcc_mask; in dbgdev_wave_reset_wavefronts() local
844 for_each_inst(xcc_id, xcc_mask) in dbgdev_wave_reset_wavefronts()
1472 uint32_t xcc_mask = dqm->dev->xcc_mask; in set_pasid_vmid_mapping() local
1475 for_each_inst(xcc_id, xcc_mask) { in set_pasid_vmid_mapping()
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H A Dkfd_device.c684 uint32_t xcc_mask = node->xcc_mask; in kfd_setup_interrupt_bitmap() local
710 for_each_inst(xcc, xcc_mask) { in kfd_setup_interrupt_bitmap()
719 for_each_inst(xcc, xcc_mask) { in kfd_setup_interrupt_bitmap()
880 &node->xcc_mask); in kgd2kfd_device_init()
883 node->xcc_mask = in kgd2kfd_device_init()
884 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; in kgd2kfd_device_init()
H A Dkfd_queue.c312 topo_dev->node_props.debug_memory_size) * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_acquire_buffers()
359 topo_dev->node_props.debug_memory_size) * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_release_buffers()
492 cu_num = props->simd_count / props->simd_per_cu / NUM_XCC(dev->gpu->xcc_mask); in kfd_queue_ctx_save_restore_size()
H A Dkfd_debug.c378 ffs(pdd->dev->xcc_mask) - 1); in kfd_dbg_set_mes_debug_mode()
471 uint32_t xcc_mask = pdd->dev->xcc_mask; in kfd_dbg_trap_set_dev_address_watch() local
488 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
1122 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); in kfd_dbg_trap_device_snapshot()
H A Dkfd_topology.c463 NUM_XCC(dev->gpu->xcc_mask)) : 0); in node_show()
543 NUM_XCC(dev->gpu->xcc_mask)); in node_show()
1108 buf[7] = (ffs(gpu->xcc_mask) - 1) | (NUM_XCC(gpu->xcc_mask) << 16); in kfd_generate_gpu_id()
1687 int num_xcc = NUM_XCC(knode->xcc_mask); in fill_in_l2_l3_pcache()
1693 start = ffs(knode->xcc_mask) - 1; in fill_in_l2_l3_pcache()
1818 start = ffs(kdev->xcc_mask) - 1; in kfd_fill_cache_non_crat_info()
1819 end = start + NUM_XCC(kdev->xcc_mask); in kfd_fill_cache_non_crat_info()
H A Dkfd_process_queue_manager.c98 ffs(pdd->dev->xcc_mask) - 1); in kfd_process_dequeue_from_device()
1043 set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->adev->gfx.xcc_mask)); in kfd_criu_restore_queue()
1125 num_xccs = NUM_XCC(q->device->xcc_mask); in pqm_debugfs_mqds()
H A Dkfd_priv.h279 uint32_t xcc_mask; /* Instance mask of XCCs present */ member
1563 pdd->dev->xcc_mask); in kfd_flush_tlb()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_1.c228 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_set_kiq_pm4_funcs()
526 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_init_rlcg_reg_access_ctrl()
570 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_rlc_init()
594 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_mec_init()
726 for (logic_xcc = 0; logic_xcc < NUM_XCC(adev->gfx.xcc_mask); logic_xcc++) { in gfx_v12_1_ih_to_xcc_inst()
931 ((1 << (i / 2)) & adev->gfx.xcc_mask)) { in gfx_v12_1_rlc_backdoor_autoload_copy_ucode()
1106 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_rlc_backdoor_autoload_enable()
1165 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_sw_init()
1280 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v12_1_sw_fini()
1383 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { in gfx_v12_1_setup_rb()
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H A Dcyan_skillfish_reg_init.c36 adev->gfx.xcc_mask = 1; in cyan_skillfish_reg_base_init()
H A Damdgpu_gfx.c213 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_compute_queue_acquire()
513 int xcc_inst = ffs(adev->gfx.xcc_mask) - 1; in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
522 num_xcc = hweight16(adev->gfx.xcc_mask); in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
1100 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_ras_error_func()
1101 uint32_t xcc_mask = GENMASK(num_xcc - 1, 0); in amdgpu_gfx_ras_error_func() local
1109 for_each_inst(i, xcc_mask) in amdgpu_gfx_ras_error_func()
1541 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_set_compute_partition()
1704 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_run_cleaner_shader()
H A Damdgpu_discovery.c847 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
1136 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1486 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1586 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
2797 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2826 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2856 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2903 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2934 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2969 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
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H A Dmes_v12_1.c1534 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_sw_init()
1581 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_sw_fini()
1770 u32 num_xcc_per_xcp, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_setup_coop_mode()
1882 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_hw_init()
1937 int xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_late_init()
2028 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_test_ring()
2135 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); in mes_v12_1_test_queue()
H A Damdgpu_gmc.c1628 uint32_t xcc_mask; in amdgpu_gmc_init_acpi_mem_ranges() local
1630 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gmc_init_acpi_mem_ranges()
1631 xcc_mask = (1U << num_xcc) - 1; in amdgpu_gmc_init_acpi_mem_ranges()
1633 for_each_inst(xcc_id, xcc_mask) { in amdgpu_gmc_init_acpi_mem_ranges()
H A Damdgpu_vm.h530 uint32_t xcc_mask);
H A Damdgpu_vm.c1709 uint32_t xcc_mask) in amdgpu_vm_flush_compute_tlb() argument
1729 for_each_inst(xcc, xcc_mask) { in amdgpu_vm_flush_compute_tlb()
H A Dgmc_v9_0.c1951 NUM_XCC(adev->gfx.xcc_mask)); in gmc_v9_0_sw_init()
H A Dsdma_v7_1.c1320 for (xcc_id = 0; xcc_id < fls(adev->gfx.xcc_mask); xcc_id++) { in sdma_v7_1_sw_init()
H A Dgfx_v6_0.c3094 adev->gfx.xcc_mask = 1; in gfx_v6_0_early_init()
H A Dgfx_v9_0.c4807 adev->gfx.xcc_mask = 1; in gfx_v9_0_early_init()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c2940 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { in smu_v13_0_6_get_gpu_metrics()