Searched refs:xcc_inst (Results 1 – 5 of 5) sorted by relevance
112 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; in mqd_symmetrically_map_cu_mask() local152 cu_info->bitmap[xcc_inst][se % 4][sh + (se / 4) * in mqd_symmetrically_map_cu_mask()
224 u32 pasid, unsigned int vmid, uint32_t xcc_inst) in kgd_gfx_v9_4_3_set_pasid_vmid_mapping() argument228 unsigned int phy_inst = GET_INST(GC, xcc_inst); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
122 int xcc_inst = dev_inst % adev->sdma.num_inst_per_xcc; in sdma_v7_1_get_reg_offset() local126 if (xcc_inst != 0) in sdma_v7_1_get_reg_offset()127 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * xcc_inst; in sdma_v7_1_get_reg_offset()130 if (xcc_inst != 0) in sdma_v7_1_get_reg_offset()131 internal_offset += SDMA1_REG_OFFSET * xcc_inst; in sdma_v7_1_get_reg_offset()
869 uint32_t xcc_inst) in amdgpu_gmc_fw_reg_write_reg_wait() argument871 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst]; in amdgpu_gmc_fw_reg_write_reg_wait()877 if (adev->mes.ring[MES_PIPE_INST(xcc_inst, 0)].sched.ready) { in amdgpu_gmc_fw_reg_write_reg_wait()879 ref, mask, xcc_inst); in amdgpu_gmc_fw_reg_write_reg_wait()
513 int xcc_inst = ffs(adev->gfx.xcc_mask) - 1; in amdgpu_gfx_mqd_symmetrically_map_cu_mask() local519 if (xcc_inst < 0) in amdgpu_gfx_mqd_symmetrically_map_cu_mask()520 xcc_inst = 0; in amdgpu_gfx_mqd_symmetrically_map_cu_mask()533 cu_info->bitmap[xcc_inst][se % 4][sh + (se / 4) * in amdgpu_gfx_mqd_symmetrically_map_cu_mask()