| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mes_v12_1.c | 42 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id);
44 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
45 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
46 static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id);
47 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id);
153 int xcc_id, int pipe, void *pkt, in mes_v12_1_submit_pkt_and_poll_completion()
159 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; in mes_v12_1_submit_pkt_and_poll_completion()
160 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; in mes_v12_1_submit_pkt_and_poll_completion()
226 xcc_id, pipe, op_str, misc_op_str); in mes_v12_1_submit_pkt_and_poll_completion()
229 xcc_id, pip in mes_v12_1_submit_pkt_and_poll_completion()
150 mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes * mes,int xcc_id,int pipe,void * pkt,int size,int api_status_off) mes_v12_1_submit_pkt_and_poll_completion() argument
287 int xcc_id = input->xcc_id; mes_v12_1_add_hw_queue() local
348 int xcc_id = input->xcc_id; mes_v12_1_remove_hw_queue() local
481 mes_v12_1_query_sched_status(struct amdgpu_mes * mes,int pipe,int xcc_id) mes_v12_1_query_sched_status() argument
500 mes_v12_1_get_rrmt(uint32_t reg,uint32_t xcc_id,struct RRMT_OPTION * rrmt_opt,uint32_t * out_reg) mes_v12_1_get_rrmt() argument
612 mes_v12_1_set_hw_resources_1(struct amdgpu_mes * mes,int pipe,int xcc_id) mes_v12_1_set_hw_resources_1() argument
648 mes_v12_1_set_hw_resources(struct amdgpu_mes * mes,int pipe,int xcc_id) mes_v12_1_set_hw_resources() argument
724 mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes * mes,int xcc_id) mes_v12_1_init_aggregated_doorbell() argument
780 mes_v12_1_enable_unmapped_doorbell_handling(struct amdgpu_mes * mes,bool enable,int xcc_id) mes_v12_1_enable_unmapped_doorbell_handling() argument
860 int xcc_id = input->xcc_id; mes_v12_1_inv_tlbs_pasid() local
902 mes_v12_1_allocate_ucode_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id) mes_v12_1_allocate_ucode_buffer() argument
937 mes_v12_1_allocate_ucode_data_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id) mes_v12_1_allocate_ucode_data_buffer() argument
972 mes_v12_1_free_ucode_buffers(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id) mes_v12_1_free_ucode_buffers() argument
986 mes_v12_1_enable(struct amdgpu_device * adev,bool enable,int xcc_id) mes_v12_1_enable() argument
1038 mes_v12_1_set_ucode_start_addr(struct amdgpu_device * adev,int xcc_id) mes_v12_1_set_ucode_start_addr() argument
1065 mes_v12_1_load_microcode(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,bool prime_icache,int xcc_id) mes_v12_1_load_microcode() argument
1130 mes_v12_1_allocate_eop_buf(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id) mes_v12_1_allocate_eop_buf() argument
1156 mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id) mes_v12_1_allocate_shared_cmd_buf() argument
1287 mes_v12_1_queue_init_register(struct amdgpu_ring * ring,int xcc_id) mes_v12_1_queue_init_register() argument
1349 mes_v12_1_kiq_enable_queue(struct amdgpu_device * adev,int xcc_id) mes_v12_1_kiq_enable_queue() argument
1376 mes_v12_1_queue_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id) mes_v12_1_queue_init() argument
1424 mes_v12_1_ring_init(struct amdgpu_device * adev,int xcc_id,int pipe) mes_v12_1_ring_init() argument
1462 mes_v12_1_kiq_ring_init(struct amdgpu_device * adev,int xcc_id) mes_v12_1_kiq_ring_init() argument
1497 mes_v12_1_mqd_sw_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id) mes_v12_1_mqd_sw_init() argument
1534 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); mes_v12_1_sw_init() local
1581 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); mes_v12_1_sw_fini() local
1630 mes_v12_1_kiq_dequeue_sched(struct amdgpu_device * adev,int xcc_id) mes_v12_1_kiq_dequeue_sched() argument
1667 mes_v12_1_kiq_setting(struct amdgpu_ring * ring,int xcc_id) mes_v12_1_kiq_setting() argument
1681 mes_v12_1_kiq_hw_init(struct amdgpu_device * adev,uint32_t xcc_id) mes_v12_1_kiq_hw_init() argument
1748 mes_v12_1_kiq_hw_fini(struct amdgpu_device * adev,uint32_t xcc_id) mes_v12_1_kiq_hw_fini() argument
1768 mes_v12_1_setup_coop_mode(struct amdgpu_device * adev,int xcc_id) mes_v12_1_setup_coop_mode() argument
1807 mes_v12_1_xcc_hw_init(struct amdgpu_ip_block * ip_block,int xcc_id) mes_v12_1_xcc_hw_init() argument
1882 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); mes_v12_1_hw_init() local
1937 int xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); mes_v12_1_late_init() local
2022 mes_v12_1_test_ring(struct amdgpu_device * adev,int xcc_id,u32 * queue_ptr,u64 fence_gpu_addr,void * fence_cpu_ptr,void * wptr_cpu_addr,u64 doorbell_idx,int queue_type) mes_v12_1_test_ring() argument
2125 mes_v12_1_test_queue(struct amdgpu_device * adev,int xcc_id,int pasid,struct amdgpu_vm * vm,u64 meta_gpu_addr,u64 queue_gpu_addr,void * ctx_ptr,int queue_type) mes_v12_1_test_queue() argument
2221 mes_v12_1_self_test(struct amdgpu_device * adev,int xcc_id) mes_v12_1_self_test() argument
[all...] |
| H A D | gfx_v12_1.c | 72 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id);
82 u32 sh_num, u32 instance, int xcc_id);
89 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
90 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
94 bool enable, int xcc_id);
159 seq, kiq_ring->xcc_id); in gfx_v12_1_kiq_unmap_queues()
269 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); in gfx_v12_1_ring_test_ring()
529 int xcc_id, num_xcc; in gfx_v12_1_init_rlcg_reg_access_ctrl()
533 for (xcc_id = 0; xcc_id < num_xc in gfx_v12_1_init_rlcg_reg_access_ctrl()
523 int xcc_id, num_xcc; gfx_v12_1_init_rlcg_reg_access_ctrl() local
626 wave_read_ind(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t wave,uint32_t address) wave_read_ind() argument
636 wave_read_regs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out) wave_read_regs() argument
650 gfx_v12_1_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields) gfx_v12_1_read_wave_data() argument
687 gfx_v12_1_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst) gfx_v12_1_read_wave_sgprs() argument
699 gfx_v12_1_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst) gfx_v12_1_read_wave_vgprs() argument
710 gfx_v12_1_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id) gfx_v12_1_select_me_pipe_q() argument
766 gfx_v12_1_compute_ring_init(struct amdgpu_device * adev,int ring_id,int xcc_id,int mec,int pipe,int queue) gfx_v12_1_compute_ring_init() argument
1141 int xcc_id, num_xcc; gfx_v12_1_sw_init() local
1306 gfx_v12_1_xcc_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id) gfx_v12_1_xcc_select_se_sh() argument
1333 gfx_v12_1_get_sa_active_bitmap(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_get_sa_active_bitmap() argument
1352 gfx_v12_1_get_rb_active_bitmap(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_get_rb_active_bitmap() argument
1381 int xcc_id; gfx_v12_1_setup_rb() local
1407 gfx_v12_1_xcc_init_compute_vmid(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_init_compute_vmid() argument
1454 gfx_v12_1_xcc_constants_init(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_constants_init() argument
1498 gfx_v12_1_xcc_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable,int xcc_id) gfx_v12_1_xcc_enable_gui_idle_interrupt() argument
1520 gfx_v12_1_xcc_init_csb(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_init_csb() argument
1535 gfx_v12_1_xcc_rlc_stop(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_rlc_stop() argument
1553 gfx_v12_1_xcc_rlc_reset(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_rlc_reset() argument
1573 gfx_v12_1_xcc_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable,int xcc_id) gfx_v12_1_xcc_rlc_smu_handshake_cntl() argument
1595 gfx_v12_1_xcc_rlc_start(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_rlc_start() argument
1617 gfx_v12_1_xcc_rlc_enable_srm(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_rlc_enable_srm() argument
1629 gfx_v12_1_xcc_load_rlcg_microcode(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_load_rlcg_microcode() argument
1654 gfx_v12_1_xcc_load_rlc_iram_dram_microcode(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_load_rlc_iram_dram_microcode() argument
1704 gfx_v12_1_xcc_rlc_load_microcode(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_rlc_load_microcode() argument
1733 gfx_v12_1_xcc_rlc_resume(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_rlc_resume() argument
1786 gfx_v12_1_xcc_config_gfx_rs64(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_config_gfx_rs64() argument
1832 gfx_v12_1_xcc_set_mec_ucode_start_addr(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_set_mec_ucode_start_addr() argument
1853 gfx_v12_1_xcc_wait_for_rlc_autoload_complete(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_wait_for_rlc_autoload_complete() argument
1889 int xcc_id; gfx_v12_1_wait_for_rlc_autoload_complete() local
1898 gfx_v12_1_xcc_cp_compute_enable(struct amdgpu_device * adev,bool enable,int xcc_id) gfx_v12_1_xcc_cp_compute_enable() argument
1936 int i, r, xcc_id; gfx_v12_1_init_cp_compute_microcode_bo() local
2000 gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_cp_compute_load_microcode_rs64() argument
2090 gfx_v12_1_xcc_kiq_setting(struct amdgpu_ring * ring,int xcc_id) gfx_v12_1_xcc_kiq_setting() argument
2105 gfx_v12_1_xcc_cp_set_doorbell_range(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_cp_set_doorbell_range() argument
2255 gfx_v12_1_xcc_kiq_init_register(struct amdgpu_ring * ring,int xcc_id) gfx_v12_1_xcc_kiq_init_register() argument
2358 gfx_v12_1_xcc_kiq_init_queue(struct amdgpu_ring * ring,int xcc_id) gfx_v12_1_xcc_kiq_init_queue() argument
2398 gfx_v12_1_xcc_kcq_init_queue(struct amdgpu_ring * ring,int xcc_id) gfx_v12_1_xcc_kcq_init_queue() argument
2428 gfx_v12_1_xcc_kiq_resume(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_kiq_resume() argument
2454 gfx_v12_1_xcc_kcq_resume(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_kcq_resume() argument
2486 int r, i, xcc_id; gfx_v12_1_xcc_cp_resume() local
2627 gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_disable_gpa_mode() argument
2641 gfx_v12_1_xcc_enable_atomics(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_enable_atomics() argument
2653 gfx_v12_1_xcc_disable_burst(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_disable_burst() argument
2660 gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_disable_early_write_ack() argument
2671 gfx_v12_1_xcc_disable_tcp_spill_cache(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_disable_tcp_spill_cache() argument
2765 gfx_v12_1_xcc_fini(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_fini() argument
2951 gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_set_safe_mode() argument
2971 gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_xcc_unset_safe_mode() argument
2988 gfx_v12_1_update_spm_vmid(struct amdgpu_device * adev,int xcc_id,struct amdgpu_ring * ring,unsigned vmid) gfx_v12_1_update_spm_vmid() argument
3064 gfx_v12_1_xcc_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable,int xcc_id) gfx_v12_1_xcc_update_coarse_grain_clock_gating() argument
3145 gfx_v12_1_xcc_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable,int xcc_id) gfx_v12_1_xcc_update_medium_grain_clock_gating() argument
3179 gfx_v12_1_xcc_update_repeater_fgcg(struct amdgpu_device * adev,bool enable,int xcc_id) gfx_v12_1_xcc_update_repeater_fgcg() argument
3200 gfx_v12_1_xcc_update_sram_fgcg(struct amdgpu_device * adev,bool enable,int xcc_id) gfx_v12_1_xcc_update_sram_fgcg() argument
3219 gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device * adev,bool enable,int xcc_id) gfx_v12_1_xcc_update_perf_clk() argument
3238 gfx_v12_1_xcc_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable,int xcc_id) gfx_v12_1_xcc_update_gfx_clock_gating() argument
3537 gfx_v12_1_xcc_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state,int xcc_id) gfx_v12_1_xcc_set_compute_eop_interrupt_state() argument
3641 int i, xcc_id; gfx_v12_1_eop_irq() local
3733 int i, xcc_id; gfx_v12_1_handle_priv_fault() local
3978 gfx_v12_1_set_user_cu_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap,int xcc_id) gfx_v12_1_set_user_cu_inactive_bitmap_per_sh() argument
3992 gfx_v12_1_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev,int xcc_id) gfx_v12_1_get_cu_active_bitmap_per_sh() argument
4010 int i, j, k, counter, xcc_id, active_cu_number = 0; gfx_v12_1_get_cu_info() local
[all...] |
| H A D | amdgpu_gfx.c | 73 int xcc_id, int mec, int pipe, int queue) in amdgpu_gfx_is_mec_queue_enabled() argument
76 adev->gfx.mec_bitmap[xcc_id].queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
272 struct amdgpu_ring *ring, int xcc_id) in amdgpu_gfx_kiq_acquire() argument
282 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap)) in amdgpu_gfx_kiq_acquire()
306 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_kiq_init_ring() argument
308 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; in amdgpu_gfx_kiq_init_ring()
318 ring->xcc_id = xcc_id; in amdgpu_gfx_kiq_init_ring()
319 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); in amdgpu_gfx_kiq_init_ring()
322 xcc_id * ade in amdgpu_gfx_kiq_init_ring()
347 amdgpu_gfx_kiq_fini(struct amdgpu_device * adev,int xcc_id) amdgpu_gfx_kiq_fini() argument
355 amdgpu_gfx_kiq_init(struct amdgpu_device * adev,unsigned int hpd_size,int xcc_id) amdgpu_gfx_kiq_init() argument
382 amdgpu_gfx_mqd_sw_init(struct amdgpu_device * adev,unsigned int mqd_size,int xcc_id) amdgpu_gfx_mqd_sw_init() argument
474 amdgpu_gfx_mqd_sw_fini(struct amdgpu_device * adev,int xcc_id) amdgpu_gfx_mqd_sw_fini() argument
555 amdgpu_gfx_disable_kcq(struct amdgpu_device * adev,int xcc_id) amdgpu_gfx_disable_kcq() argument
605 amdgpu_gfx_disable_kgq(struct amdgpu_device * adev,int xcc_id) amdgpu_gfx_disable_kgq() argument
672 amdgpu_gfx_mes_enable_kcq(struct amdgpu_device * adev,int xcc_id) amdgpu_gfx_mes_enable_kcq() argument
711 amdgpu_gfx_enable_kcq(struct amdgpu_device * adev,int xcc_id) amdgpu_gfx_enable_kcq() argument
775 amdgpu_gfx_enable_kgq(struct amdgpu_device * adev,int xcc_id) amdgpu_gfx_enable_kgq() argument
1097 amdgpu_gfx_ras_error_func(struct amdgpu_device * adev,void * ras_error_status,void (* func)(struct amdgpu_device * adev,void * ras_error_status,int xcc_id)) amdgpu_gfx_ras_error_func() argument
1113 amdgpu_kiq_rreg(struct amdgpu_device * adev,uint32_t reg,uint32_t xcc_id) amdgpu_kiq_rreg() argument
1187 amdgpu_kiq_wreg(struct amdgpu_device * adev,uint32_t reg,uint32_t v,uint32_t xcc_id) amdgpu_kiq_wreg() argument
1508 amdgpu_gfx_is_master_xcc(struct amdgpu_device * adev,int xcc_id) amdgpu_gfx_is_master_xcc() argument
1707 int i, r, xcc_id; amdgpu_gfx_run_cleaner_shader() local
[all...] |
| H A D | amdgpu_umr.h | 46 u32 xcc_id; member
50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
|
| H A D | sdma_v7_1.c | 121 int xcc_id = adev->sdma.instance[instance].xcc_id; in sdma_v7_1_get_reg_offset() local
125 base = adev->reg_offset[GC_HWIP][xcc_id][1]; in sdma_v7_1_get_reg_offset()
129 base = adev->reg_offset[GC_HWIP][xcc_id][0]; in sdma_v7_1_get_reg_offset()
1304 u32 xcc_id; in sdma_v7_1_sw_init()
1320 for (xcc_id = 0; xcc_id < fls(adev->gfx.xcc_mask); xcc_id++) { in sdma_v7_1_sw_init()
1321 if (adev->sdma.instance[i].xcc_id == GET_INST(GC, xcc_id)) in sdma_v7_1_sw_init()
1305 u32 xcc_id; sdma_v7_1_sw_init() local
1524 int inst, instances, queue, xcc_id = 0; sdma_v7_1_process_trap_irq() local
[all...] |
| H A D | gfx_v9_0.h | 30 u32 instance, int xcc_id);
|
| H A D | gmc_v9_0.c | 559 int ret, xcc_id = 0; in gmc_v9_0_process_interrupt() local
576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, in gmc_v9_0_process_interrupt()
578 if (xcc_id < 0) in gmc_v9_0_process_interrupt()
579 xcc_id = 0; in gmc_v9_0_process_interrupt()
581 vmhub = xcc_id; in gmc_v9_0_process_interrupt()
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| H A D | gfx_v12_0.c | 278 u32 sh_num, u32 instance, int xcc_id);
287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
845 uint32_t xcc_id, in gfx_v12_0_read_wave_data() argument
882 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_sgprs() argument
894 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_vgprs() argument
905 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v12_0_select_me_pipe_q() argument
1407 int xcc_id = 0; in gfx_v12_0_sw_init() local
1580 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v12_0_sw_init()
1675 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_0_select_se_sh() argument
3959 gfx_v12_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id) gfx_v12_0_set_safe_mode() argument
3979 gfx_v12_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id) gfx_v12_0_unset_safe_mode() argument
4004 gfx_v12_0_update_spm_vmid(struct amdgpu_device * adev,int xcc_id,struct amdgpu_ring * ring,unsigned vmid) gfx_v12_0_update_spm_vmid() argument
[all...] |
| H A D | mes_v11_0.c | 66 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
67 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
1572 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v11_0_kiq_hw_init()
1627 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v11_0_kiq_hw_fini()
1570 mes_v11_0_kiq_hw_init(struct amdgpu_device * adev,uint32_t xcc_id) mes_v11_0_kiq_hw_init() argument
1625 mes_v11_0_kiq_hw_fini(struct amdgpu_device * adev,uint32_t xcc_id) mes_v11_0_kiq_hw_fini() argument
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| H A D | mes_v12_0.c | 45 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
46 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
1740 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v12_0_kiq_hw_init() argument
1802 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v12_0_kiq_hw_fini() argument
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| H A D | gfx_v9_0.c | 924 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
925 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
1046 uint32_t xcc_id, uint32_t vmid) in gfx_v9_0_kiq_reset_hw_queue() argument
1052 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1074 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1955 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) in gfx_v9_0_read_wave_data() argument
1976 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_sgprs() argument
1985 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_vgprs() argument
1996 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v9_0_select_me_pipe_q() argument
2217 int xcc_id in gfx_v9_0_sw_init() local
2503 gfx_v9_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id) gfx_v9_0_select_se_sh() argument
4899 gfx_v9_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id) gfx_v9_0_set_safe_mode() argument
4916 gfx_v9_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id) gfx_v9_0_unset_safe_mode() argument
5178 gfx_v9_0_update_spm_vmid(struct amdgpu_device * adev,int xcc_id,struct amdgpu_ring * ring,unsigned int vmid) gfx_v9_0_update_spm_vmid() argument
[all...] |
| H A D | amdgpu_gmc.c | 1642 int num_xcc, xcc_id; in amdgpu_gmc_init_acpi_mem_ranges()
1648 for_each_inst(xcc_id, xcc_mask) { in amdgpu_gmc_init_acpi_mem_ranges()
1649 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); in amdgpu_gmc_init_acpi_mem_ranges()
1627 int num_xcc, xcc_id; amdgpu_gmc_init_acpi_mem_ranges() local
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| H A D | amdgpu_acpi.c | 1225 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, in amdgpu_acpi_get_mem_info() argument
1242 if (xcc_info->phy_id == xcc_id) { in amdgpu_acpi_get_mem_info()
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| H A D | gfx_v11_0.c | 344 u32 sh_num, u32 instance, int xcc_id);
355 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
356 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); in gfx11_kiq_set_resources()
1007 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) in gfx_v11_0_read_wave_data()
1033 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_sgprs()
1044 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_vgprs()
1055 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
1597 int xcc_id = 0; in gfx_v11_0_sw_init()
1883 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v11_0_sw_init()
1985 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh()
1003 gfx_v11_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields) gfx_v11_0_read_wave_data() argument
1029 gfx_v11_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst) gfx_v11_0_read_wave_sgprs() argument
1040 gfx_v11_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst) gfx_v11_0_read_wave_vgprs() argument
1051 gfx_v11_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id) gfx_v11_0_select_me_pipe_q() argument
1592 int xcc_id = 0; gfx_v11_0_sw_init() local
1979 gfx_v11_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id) gfx_v11_0_select_se_sh() argument
5380 gfx_v11_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id) gfx_v11_0_set_safe_mode() argument
5399 gfx_v11_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id) gfx_v11_0_unset_safe_mode() argument
5652 gfx_v11_0_update_spm_vmid(struct amdgpu_device * adev,int xcc_id,struct amdgpu_ring * ring,unsigned vmid) gfx_v11_0_update_spm_vmid() argument
[all...] |
| H A D | amdgpu.h | 1521 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1536 int xcc_id,
1567 amdgpu_acpi_get_mem_info(struct amdgpu_device * adev,int xcc_id,struct amdgpu_numa_info * numa_info) amdgpu_acpi_get_mem_info() argument
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| H A D | gfx_v6_0.c | 1305 u32 sh_num, u32 instance, int xcc_id) in gfx_v6_0_select_se_sh() argument
3034 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v6_0_read_wave_data() argument
3059 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v6_0_read_wave_sgprs() argument
3069 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v6_0_select_me_pipe_q() argument
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| H A D | amdgpu_vm.c | 846 adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring, job->vmid); in amdgpu_vm_flush()
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| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_mqd_manager_v9.c | 641 int xcc_id, err = 0, inst = 0; in hiq_load_mqd_kiq_v9_4_3()
645 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
649 p->doorbell_off, xcc_id); in destroy_hiq_mqd_v9_4_3()
665 int xcc_id, err = 0, inst = 0; in destroy_hiq_mqd_v9_4_3()
670 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
676 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id); in check_preemption_failed_v9_4_3()
691 int inst = 0, xcc_id; in check_preemption_failed_v9_4_3()
695 for_each_inst(xcc_id, xcc_mask) { in get_xcc_mqd()
872 int xcc_id, err = 0, inst = 0; in destroy_mqd_v9_4_3()
880 for_each_inst(xcc_id, xcc_mas in destroy_mqd_v9_4_3()
630 int xcc_id, err = 0, inst = 0; hiq_load_mqd_kiq_v9_4_3() local
654 int xcc_id, err = 0, inst = 0; destroy_hiq_mqd_v9_4_3() local
680 int inst = 0, xcc_id; check_preemption_failed_v9_4_3() local
861 int xcc_id, err = 0, inst = 0; destroy_mqd_v9_4_3() local
891 int xcc_id, err = 0, inst = 0; load_mqd_v9_4_3() local
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| H A D | kfd_device_queue_manager.c | 156 int xcc_id; in program_sh_mem_settings()
158 for_each_inst(xcc_id, xcc_mask)
162 qpd->sh_mem_bases, xcc_id); in kfd_hws_hang()
266 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in add_queue_mes()
304 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in remove_queue_mes()
664 int xcc_id; in create_queue_nocpsch()
667 for_each_inst(xcc_id, xcc_mask) in create_queue_nocpsch()
670 qpd->tma_addr, xcc_id); in create_queue_nocpsch()
938 int xcc_id; in destroy_queue_nocpsch()
984 for_each_inst(xcc_id, xcc_mas in update_queue()
150 int xcc_id; program_sh_mem_settings() local
527 int xcc_id; program_trap_handler_settings() local
801 int xcc_id; dbgdev_wave_reset_wavefronts() local
1476 int xcc_id, ret = 0; set_pasid_vmid_mapping() local
1491 unsigned int i, xcc_id; init_interrupts() local
2167 int xcc_id; detect_queue_hang() local
3689 int r = 0, xcc_id; dqm_debugfs_hqds() local
[all...] |
| H A D | kfd_debug.c | 470 int xcc_id, r = kfd_dbg_get_dev_watch_id(pdd, watch_id); in kfd_dbg_trap_set_dev_address_watch() local
488 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
496 xcc_id); in kfd_dbg_trap_set_dev_address_watch()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_6_ppt.c | 1279 int xcc_id; in smu_v13_0_6_get_smu_metrics_data()
1294 xcc_id = GET_INST(GC, 0); in smu_v13_0_6_get_smu_metrics_data()
1295 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]); in smu_v13_0_6_get_smu_metrics_data()
2780 int ret = 0, xcc_id, inst, i, j; in smu_v13_0_6_get_gpu_metrics()
2829 xcc_id = GET_INST(GC, i); in smu_v13_0_6_get_gpu_metrics()
2830 if (xcc_id >= 0) in smu_v13_0_6_get_gpu_metrics()
2832 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]); in smu_v13_0_6_get_gpu_metrics()
1275 int xcc_id; smu_v13_0_6_get_smu_metrics_data() local
2776 int ret = 0, xcc_id, inst, i, j; smu_v13_0_6_get_gpu_metrics() local
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