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Searched refs:xcc_id (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v12_1.c42 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id);
44 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
45 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
46 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id);
156 int xcc_id, int pipe, void *pkt, in mes_v12_1_submit_pkt_and_poll_completion() argument
162 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; in mes_v12_1_submit_pkt_and_poll_completion()
163 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; in mes_v12_1_submit_pkt_and_poll_completion()
229 xcc_id, pipe, op_str, misc_op_str); in mes_v12_1_submit_pkt_and_poll_completion()
232 xcc_id, pipe, op_str); in mes_v12_1_submit_pkt_and_poll_completion()
235 xcc_id, pipe, x_pkt->header.opcode); in mes_v12_1_submit_pkt_and_poll_completion()
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H A Dgfx_v12_1.c193 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id);
203 u32 sh_num, u32 instance, int xcc_id);
210 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
211 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
215 bool enable, int xcc_id);
280 seq, kiq_ring->xcc_id); in gfx_v12_1_kiq_unmap_queues()
390 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); in gfx_v12_1_ring_test_ring()
650 int xcc_id, num_xcc; in gfx_v12_1_init_rlcg_reg_access_ctrl() local
654 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { in gfx_v12_1_init_rlcg_reg_access_ctrl()
655 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; in gfx_v12_1_init_rlcg_reg_access_ctrl()
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H A Dgfx_v9_4_3.c171 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
172 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
292 uint32_t xcc_id, uint32_t vmid) in gfx_v9_4_3_kiq_reset_hw_queue() argument
298 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); in gfx_v9_4_3_kiq_reset_hw_queue()
300 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); in gfx_v9_4_3_kiq_reset_hw_queue()
303 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v9_4_3_kiq_reset_hw_queue()
304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v9_4_3_kiq_reset_hw_queue()
307 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_kiq_reset_hw_queue()
320 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); in gfx_v9_4_3_kiq_reset_hw_queue()
425 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_ring_test_ring()
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H A Damdgpu_mes.h73 #define MES_PIPE_INST(xcc_id, pipe_id) \ argument
74 (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id)
138 uint32_t xcc_id);
140 uint32_t xcc_id);
254 uint32_t xcc_id; member
288 uint32_t xcc_id; member
297 uint32_t xcc_id; member
307 uint32_t xcc_id; member
318 uint32_t xcc_id; member
328 uint32_t xcc_id; member
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H A Damdgpu_gfx.c75 int xcc_id, int mec, int pipe, int queue) in amdgpu_gfx_is_mec_queue_enabled() argument
78 adev->gfx.mec_bitmap[xcc_id].queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
274 struct amdgpu_ring *ring, int xcc_id) in amdgpu_gfx_kiq_acquire() argument
284 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap)) in amdgpu_gfx_kiq_acquire()
308 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_kiq_init_ring() argument
310 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; in amdgpu_gfx_kiq_init_ring()
320 ring->xcc_id = xcc_id; in amdgpu_gfx_kiq_init_ring()
321 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); in amdgpu_gfx_kiq_init_ring()
324 xcc_id * adev->doorbell_index.xcc_doorbell_range) in amdgpu_gfx_kiq_init_ring()
327 r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id); in amdgpu_gfx_kiq_init_ring()
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H A Damdgpu_umr.h46 u32 xcc_id; member
50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Dsdma_v7_1.c121 int xcc_id = adev->sdma.instance[instance].xcc_id; in sdma_v7_1_get_reg_offset() local
125 base = adev->reg_offset[GC_HWIP][xcc_id][1]; in sdma_v7_1_get_reg_offset()
129 base = adev->reg_offset[GC_HWIP][xcc_id][0]; in sdma_v7_1_get_reg_offset()
1287 u32 xcc_id; in sdma_v7_1_sw_init() local
1303 for (xcc_id = 0; xcc_id < fls(adev->gfx.xcc_mask); xcc_id++) { in sdma_v7_1_sw_init()
1304 if (adev->sdma.instance[i].xcc_id == GET_INST(GC, xcc_id)) in sdma_v7_1_sw_init()
1309 xcc_id, GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc, in sdma_v7_1_sw_init()
1315 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); in sdma_v7_1_sw_init()
1316 sprintf(ring->name, "sdma%d.%d", xcc_id, in sdma_v7_1_sw_init()
1512 int inst, instances, queue, xcc_id = 0; in sdma_v7_1_process_trap_irq() local
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H A Dgmc_v12_1.c113 int ret, xcc_id = 0; in gmc_v12_1_process_interrupt() local
135 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, in gmc_v12_1_process_interrupt()
137 if (xcc_id < 0) in gmc_v12_1_process_interrupt()
138 xcc_id = 0; in gmc_v12_1_process_interrupt()
140 vmhub = xcc_id; in gmc_v12_1_process_interrupt()
417 input.xcc_id = inst; in gmc_v12_1_flush_gpu_tlb_pasid()
H A Dgfx_v9_0.h30 u32 instance, int xcc_id);
H A Dgfx_v12_0.c278 u32 sh_num, u32 instance, int xcc_id);
287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
846 uint32_t xcc_id, in gfx_v12_0_read_wave_data() argument
883 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_sgprs() argument
895 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_vgprs() argument
906 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v12_0_select_me_pipe_q() argument
1409 int xcc_id = 0; in gfx_v12_0_sw_init() local
1582 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v12_0_sw_init()
1686 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_0_select_se_sh() argument
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H A Dgfx_v9_0.c924 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
925 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
1046 uint32_t xcc_id, uint32_t vmid) in gfx_v9_0_kiq_reset_hw_queue() argument
1052 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1074 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1955 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v9_0_read_wave_data() argument
1976 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_sgprs() argument
1985 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_vgprs() argument
1996 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v9_0_select_me_pipe_q() argument
2218 int xcc_id = 0; in gfx_v9_0_sw_init() local
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H A Damdgpu_gmc.c1635 int num_xcc, xcc_id; in amdgpu_gmc_init_acpi_mem_ranges() local
1641 for_each_inst(xcc_id, xcc_mask) { in amdgpu_gmc_init_acpi_mem_ranges()
1642 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); in amdgpu_gmc_init_acpi_mem_ranges()
H A Dmes_v11_0.c70 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
71 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
1877 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v11_0_kiq_hw_init() argument
1932 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v11_0_kiq_hw_fini() argument
H A Dmes_v12_0.c45 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
46 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
1956 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v12_0_kiq_hw_init() argument
2018 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v12_0_kiq_hw_fini() argument
H A Dgfx_v11_0.c352 u32 sh_num, u32 instance, int xcc_id);
363 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
364 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
1016 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v11_0_read_wave_data() argument
1042 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_sgprs() argument
1053 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_vgprs() argument
1064 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v11_0_select_me_pipe_q() argument
1609 int xcc_id = 0; in gfx_v11_0_sw_init() local
1900 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v11_0_sw_init()
2011 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh() argument
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H A Dgfx_v8_0.c1897 int xcc_id = 0; in gfx_v8_0_sw_init() local
2019 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v8_0_sw_init()
3402 int xcc_id) in gfx_v8_0_select_se_sh() argument
3425 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v8_0_select_me_pipe_q() argument
5089 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v8_0_read_wave_data() argument
5114 static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v8_0_read_wave_sgprs() argument
5445 static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v8_0_set_safe_mode() argument
5472 static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v8_0_unset_safe_mode() argument
5489 static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, in gfx_v8_0_update_spm_vmid() argument
H A Dgfx_v10_0.c3686 u32 sh_num, u32 instance, int xcc_id);
3823 uint32_t xcc_id, uint32_t vmid) in gfx_v10_0_kiq_reset_hw_queue() argument
3830 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); in gfx_v10_0_kiq_reset_hw_queue()
4498 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v10_0_read_wave_data() argument
4526 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_sgprs() argument
4537 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_vgprs() argument
4548 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v10_0_select_me_pipe_q() argument
4757 int xcc_id = 0; in gfx_v10_0_sw_init() local
4973 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v10_0_sw_init()
5059 u32 sh_num, u32 instance, int xcc_id) in gfx_v10_0_select_se_sh() argument
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c651 int xcc_id, err = 0, inst = 0; in hiq_load_mqd_kiq_v9_4_3() local
655 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
659 p->doorbell_off, xcc_id); in hiq_load_mqd_kiq_v9_4_3()
675 int xcc_id, err = 0, inst = 0; in destroy_hiq_mqd_v9_4_3() local
680 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
686 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id); in destroy_hiq_mqd_v9_4_3()
701 int inst = 0, xcc_id; in check_preemption_failed_v9_4_3() local
705 for_each_inst(xcc_id, xcc_mask) { in check_preemption_failed_v9_4_3()
906 int xcc_id, err = 0, inst = 0; in destroy_mqd_v9_4_3() local
914 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v9_4_3()
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H A Dkfd_mqd_manager_v12_1.c536 int xcc_id, err, inst = 0; in destroy_mqd_v12_1() local
544 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v12_1()
548 queue_id, xcc_id); in destroy_mqd_v12_1()
566 int xcc_id, err, inst = 0; in load_mqd_v12_1() local
570 for_each_inst(xcc_id, xcc_mask) { in load_mqd_v12_1()
575 xcc_id); in load_mqd_v12_1()