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Searched refs:xcc_id (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v12_1.c42 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id);
44 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
45 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
46 static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id);
150 int xcc_id, int pipe, void *pkt, in mes_v12_1_submit_pkt_and_poll_completion() argument
156 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; in mes_v12_1_submit_pkt_and_poll_completion()
157 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; in mes_v12_1_submit_pkt_and_poll_completion()
223 xcc_id, pipe, op_str, misc_op_str); in mes_v12_1_submit_pkt_and_poll_completion()
226 xcc_id, pipe, op_str); in mes_v12_1_submit_pkt_and_poll_completion()
229 xcc_id, pipe, x_pkt->header.opcode); in mes_v12_1_submit_pkt_and_poll_completion()
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H A Dgfx_v12_1.c72 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id);
82 u32 sh_num, u32 instance, int xcc_id);
89 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
90 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
94 bool enable, int xcc_id);
159 seq, kiq_ring->xcc_id); in gfx_v12_1_kiq_unmap_queues()
269 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); in gfx_v12_1_ring_test_ring()
523 int xcc_id, num_xcc; in gfx_v12_1_init_rlcg_reg_access_ctrl() local
527 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { in gfx_v12_1_init_rlcg_reg_access_ctrl()
528 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; in gfx_v12_1_init_rlcg_reg_access_ctrl()
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H A Damdgpu_gfx.c73 int xcc_id, int mec, int pipe, int queue) in amdgpu_gfx_is_mec_queue_enabled() argument
76 adev->gfx.mec_bitmap[xcc_id].queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
272 struct amdgpu_ring *ring, int xcc_id) in amdgpu_gfx_kiq_acquire() argument
282 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap)) in amdgpu_gfx_kiq_acquire()
306 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_kiq_init_ring() argument
308 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; in amdgpu_gfx_kiq_init_ring()
318 ring->xcc_id = xcc_id; in amdgpu_gfx_kiq_init_ring()
319 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); in amdgpu_gfx_kiq_init_ring()
322 xcc_id * adev->doorbell_index.xcc_doorbell_range) in amdgpu_gfx_kiq_init_ring()
325 r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id); in amdgpu_gfx_kiq_init_ring()
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H A Damdgpu_umr.h46 u32 xcc_id; member
50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Dsdma_v7_1.c121 int xcc_id = adev->sdma.instance[instance].xcc_id; in sdma_v7_1_get_reg_offset() local
125 base = adev->reg_offset[GC_HWIP][xcc_id][1]; in sdma_v7_1_get_reg_offset()
129 base = adev->reg_offset[GC_HWIP][xcc_id][0]; in sdma_v7_1_get_reg_offset()
1305 u32 xcc_id; in sdma_v7_1_sw_init() local
1320 for (xcc_id = 0; xcc_id < fls(adev->gfx.xcc_mask); xcc_id++) { in sdma_v7_1_sw_init()
1321 if (adev->sdma.instance[i].xcc_id == GET_INST(GC, xcc_id)) in sdma_v7_1_sw_init()
1326 xcc_id, GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc, in sdma_v7_1_sw_init()
1332 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); in sdma_v7_1_sw_init()
1333 sprintf(ring->name, "sdma%d.%d", xcc_id, in sdma_v7_1_sw_init()
1523 int inst, instances, queue, xcc_id = 0; in sdma_v7_1_process_trap_irq() local
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H A Dgfx_v9_0.h30 u32 instance, int xcc_id);
H A Dgmc_v9_0.c559 int ret, xcc_id = 0; in gmc_v9_0_process_interrupt() local
576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, in gmc_v9_0_process_interrupt()
578 if (xcc_id < 0) in gmc_v9_0_process_interrupt()
579 xcc_id = 0; in gmc_v9_0_process_interrupt()
581 vmhub = xcc_id; in gmc_v9_0_process_interrupt()
H A Dgfx_v12_0.c278 u32 sh_num, u32 instance, int xcc_id);
287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
838 uint32_t xcc_id, in gfx_v12_0_read_wave_data() argument
875 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_sgprs() argument
887 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_vgprs() argument
898 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v12_0_select_me_pipe_q() argument
1400 int xcc_id = 0; in gfx_v12_0_sw_init() local
1573 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v12_0_sw_init()
1668 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_0_select_se_sh() argument
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H A Dmes_v11_0.c64 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
65 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
1570 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v11_0_kiq_hw_init() argument
1625 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v11_0_kiq_hw_fini() argument
H A Dmes_v12_0.c45 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
46 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
1740 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v12_0_kiq_hw_init() argument
1802 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) in mes_v12_0_kiq_hw_fini() argument
H A Dgfx_v9_0.c924 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
925 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
1046 uint32_t xcc_id, uint32_t vmid) in gfx_v9_0_kiq_reset_hw_queue() argument
1052 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1074 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1955 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v9_0_read_wave_data() argument
1976 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_sgprs() argument
1985 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_vgprs() argument
1996 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v9_0_select_me_pipe_q() argument
2217 int xcc_id = 0; in gfx_v9_0_sw_init() local
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H A Damdgpu_gmc.c1627 int num_xcc, xcc_id; in amdgpu_gmc_init_acpi_mem_ranges() local
1633 for_each_inst(xcc_id, xcc_mask) { in amdgpu_gmc_init_acpi_mem_ranges()
1634 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); in amdgpu_gmc_init_acpi_mem_ranges()
H A Damdgpu_acpi.c1225 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, in amdgpu_acpi_get_mem_info() argument
1242 if (xcc_info->phy_id == xcc_id) { in amdgpu_acpi_get_mem_info()
H A Dgfx_v11_0.c340 u32 sh_num, u32 instance, int xcc_id);
351 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
352 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
1003 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v11_0_read_wave_data() argument
1029 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_sgprs() argument
1040 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_vgprs() argument
1051 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v11_0_select_me_pipe_q() argument
1592 int xcc_id = 0; in gfx_v11_0_sw_init() local
1877 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v11_0_sw_init()
1979 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh() argument
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H A Dgfx_v6_0.c1305 u32 sh_num, u32 instance, int xcc_id) in gfx_v6_0_select_se_sh() argument
3034 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v6_0_read_wave_data() argument
3059 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v6_0_read_wave_sgprs() argument
3069 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v6_0_select_me_pipe_q() argument
H A Damdgpu_vm.c858 adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring, job->vmid); in amdgpu_vm_flush()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c625 int xcc_id, err = 0, inst = 0; in hiq_load_mqd_kiq_v9_4_3() local
629 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
633 p->doorbell_off, xcc_id); in hiq_load_mqd_kiq_v9_4_3()
649 int xcc_id, err = 0, inst = 0; in destroy_hiq_mqd_v9_4_3() local
654 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
660 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id); in destroy_hiq_mqd_v9_4_3()
675 int inst = 0, xcc_id; in check_preemption_failed_v9_4_3() local
679 for_each_inst(xcc_id, xcc_mask) { in check_preemption_failed_v9_4_3()
856 int xcc_id, err = 0, inst = 0; in destroy_mqd_v9_4_3() local
864 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v9_4_3()
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H A Dkfd_device_queue_manager.c150 int xcc_id; in program_sh_mem_settings() local
152 for_each_inst(xcc_id, xcc_mask) in program_sh_mem_settings()
156 qpd->sh_mem_bases, xcc_id); in program_sh_mem_settings()
260 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in add_queue_mes()
291 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in remove_queue_mes()
524 int xcc_id; in program_trap_handler_settings() local
527 for_each_inst(xcc_id, xcc_mask) in program_trap_handler_settings()
530 qpd->tma_addr, xcc_id); in program_trap_handler_settings()
798 int xcc_id; in dbgdev_wave_reset_wavefronts() local
844 for_each_inst(xcc_id, xcc_mask) in dbgdev_wave_reset_wavefronts()
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H A Dkfd_debug.c470 int xcc_id, r = kfd_dbg_get_dev_watch_id(pdd, watch_id); in kfd_dbg_trap_set_dev_address_watch() local
488 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
496 xcc_id); in kfd_dbg_trap_set_dev_address_watch()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c1275 int xcc_id; in smu_v13_0_6_get_smu_metrics_data() local
1290 xcc_id = GET_INST(GC, 0); in smu_v13_0_6_get_smu_metrics_data()
1291 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]); in smu_v13_0_6_get_smu_metrics_data()
2776 int ret = 0, xcc_id, inst, i, j; in smu_v13_0_6_get_gpu_metrics() local
2825 xcc_id = GET_INST(GC, i); in smu_v13_0_6_get_gpu_metrics()
2826 if (xcc_id >= 0) in smu_v13_0_6_get_gpu_metrics()
2828 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]); in smu_v13_0_6_get_gpu_metrics()