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Searched refs:xcc_id (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.h145 uint32_t xcc_id, uint32_t vmid);
291 u32 sh_num, u32 instance, int xcc_id);
292 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
294 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
297 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
301 u32 queue, u32 vmid, u32 xcc_id);
495 …elect_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (… argument
496 …_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe)… argument
516 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id);
520 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
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H A Damdgpu_gfx.c71 int xcc_id, int mec, int pipe, int queue) in amdgpu_gfx_is_mec_queue_enabled() argument
74 adev->gfx.mec_bitmap[xcc_id].queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
266 struct amdgpu_ring *ring, int xcc_id) in amdgpu_gfx_kiq_acquire() argument
276 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap)) in amdgpu_gfx_kiq_acquire()
300 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_kiq_init_ring() argument
302 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; in amdgpu_gfx_kiq_init_ring()
312 ring->xcc_id = xcc_id; in amdgpu_gfx_kiq_init_ring()
313 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); in amdgpu_gfx_kiq_init_ring()
316 xcc_id * adev->doorbell_index.xcc_doorbell_range) in amdgpu_gfx_kiq_init_ring()
319 r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id); in amdgpu_gfx_kiq_init_ring()
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H A Damdgpu_rlc.h236 void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id);
237 void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);
339 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id);
340 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id);
H A Damdgpu_umr.h46 u32 xcc_id; member
50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Damdgpu_rlc.c38 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_rlc_enter_safe_mode() argument
40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_rlc_exit_safe_mode() argument
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
H A Damdgpu_virt.h393 u32 acc_flags, u32 hwip, u32 xcc_id);
395 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
404 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
H A Dgfx_v9_0.h30 u32 instance, int xcc_id);
H A Damdgpu_debugfs.c267 rd->id.grbm.instance, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
273 rd->id.srbm.queue, rd->id.srbm.vmid, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
286 amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, value, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
299 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
304 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
358 rd->id.xcc_id = 0; in amdgpu_debugfs_regs2_ioctl()
429 amdgpu_gfx_select_se_sh(adev, rd->id.se, rd->id.sh, rd->id.cu, rd->id.xcc_id); in amdgpu_debugfs_gprwave_read()
434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
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H A Damdgpu_virt.c1009 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) in amdgpu_virt_rlcg_reg_rw() argument
1027 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
1035 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_reg_rw()
1107 u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_wreg() argument
1116 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); in amdgpu_sriov_wreg()
1127 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_rreg() argument
1136 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); in amdgpu_sriov_rreg()
H A Daqua_vanjaram.c173 aqua_vanjaram_set_xcp_id(adev, ring->xcc_id, ring); in aqua_vanjaram_update_partition_sched_list()
708 int xcc_id, uint8_t *mem_id) in __aqua_vanjaram_get_xcp_mem_id() argument
711 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; in __aqua_vanjaram_get_xcp_mem_id()
723 int r, i, xcc_id; in aqua_vanjaram_get_xcp_mem_id() local
743 xcc_id = ffs(xcc_mask) - 1; in aqua_vanjaram_get_xcp_mem_id()
745 return __aqua_vanjaram_get_xcp_mem_id(adev, xcc_id, mem_id); in aqua_vanjaram_get_xcp_mem_id()
747 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); in aqua_vanjaram_get_xcp_mem_id()
H A Dgmc_v9_0.c559 int ret, xcc_id = 0; in gmc_v9_0_process_interrupt() local
576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, in gmc_v9_0_process_interrupt()
578 if (xcc_id < 0) in gmc_v9_0_process_interrupt()
579 xcc_id = 0; in gmc_v9_0_process_interrupt()
581 vmhub = xcc_id; in gmc_v9_0_process_interrupt()
1923 int num_xcc, xcc_id; in gmc_v9_0_init_acpi_mem_ranges() local
1929 for_each_inst(xcc_id, xcc_mask) { in gmc_v9_0_init_acpi_mem_ranges()
1930 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); in gmc_v9_0_init_acpi_mem_ranges()
H A Dsoc15.h110 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);
H A Dgfx_v12_0.c230 u32 sh_num, u32 instance, int xcc_id);
240 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
241 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
798 uint32_t xcc_id, in gfx_v12_0_read_wave_data() argument
835 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_sgprs() argument
847 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_vgprs() argument
858 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v12_0_select_me_pipe_q() argument
1326 int xcc_id = 0; in gfx_v12_0_sw_init() local
1453 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v12_0_sw_init()
1548 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_0_select_se_sh() argument
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H A Damdgpu_mes.h259 uint32_t xcc_id; member
H A Dgfx_v9_0.c897 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
898 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
1019 uint32_t xcc_id, uint32_t vmid) in gfx_v9_0_kiq_reset_hw_queue() argument
1025 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1047 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1943 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v9_0_read_wave_data() argument
1964 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_sgprs() argument
1973 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_vgprs() argument
1984 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v9_0_select_me_pipe_q() argument
2204 int xcc_id = 0; in gfx_v9_0_sw_init() local
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H A Damdgpu_device.c761 uint32_t xcc_id) in amdgpu_device_xcc_rreg() argument
775 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_rreg()
779 ret = amdgpu_kiq_rreg(adev, reg, xcc_id); in amdgpu_device_xcc_rreg()
862 uint32_t xcc_id) in amdgpu_mm_wreg_mmio_rlc() argument
871 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id); in amdgpu_mm_wreg_mmio_rlc()
892 uint32_t acc_flags, uint32_t xcc_id) in amdgpu_device_xcc_wreg() argument
906 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_wreg()
910 amdgpu_kiq_wreg(adev, reg, v, xcc_id); in amdgpu_device_xcc_wreg()
H A Dgfx_v11_0.c279 u32 sh_num, u32 instance, int xcc_id);
290 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
291 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
975 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v11_0_read_wave_data() argument
1001 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_sgprs() argument
1012 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_vgprs() argument
1023 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v11_0_select_me_pipe_q() argument
1546 int xcc_id = 0; in gfx_v11_0_sw_init() local
1721 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v11_0_sw_init()
1823 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh() argument
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H A Damdgpu_ring.h262 u32 xcc_id; member
H A Dgfx_v7_0.c1551 int xcc_id) in gfx_v7_0_select_se_sh() argument
3324 static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v7_0_set_safe_mode() argument
3346 static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v7_0_unset_safe_mode() argument
4074 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v7_0_read_wave_data() argument
4099 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v7_0_read_wave_sgprs() argument
4109 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v7_0_select_me_pipe_q() argument
H A Dgfx_v8_0.c1900 int xcc_id = 0; in gfx_v8_0_sw_init() local
2022 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v8_0_sw_init()
3395 int xcc_id) in gfx_v8_0_select_se_sh() argument
3418 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v8_0_select_me_pipe_q() argument
5222 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v8_0_read_wave_data() argument
5247 static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v8_0_read_wave_sgprs() argument
5542 static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v8_0_set_safe_mode() argument
5569 static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v8_0_unset_safe_mode() argument
H A Dgfx_v10_0.c3657 u32 sh_num, u32 instance, int xcc_id);
4438 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v10_0_read_wave_data() argument
4466 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_sgprs() argument
4477 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_vgprs() argument
4488 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v10_0_select_me_pipe_q() argument
4695 int xcc_id = 0; in gfx_v10_0_sw_init() local
4840 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v10_0_sw_init()
4926 u32 sh_num, u32 instance, int xcc_id) in gfx_v10_0_select_se_sh() argument
7780 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v10_0_set_safe_mode() argument
7821 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v10_0_unset_safe_mode() argument
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c572 int xcc_id, err, inst = 0; in hiq_load_mqd_kiq_v9_4_3() local
576 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
580 p->doorbell_off, xcc_id); in hiq_load_mqd_kiq_v9_4_3()
596 int xcc_id, err, inst = 0; in destroy_hiq_mqd_v9_4_3() local
601 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
607 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id); in destroy_hiq_mqd_v9_4_3()
622 int inst = 0, xcc_id; in check_preemption_failed_v9_4_3() local
626 for_each_inst(xcc_id, xcc_mask) { in check_preemption_failed_v9_4_3()
752 int xcc_id, err, inst = 0; in destroy_mqd_v9_4_3() local
760 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v9_4_3()
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H A Dkfd_device_queue_manager.h224 int xcc_id; member
H A Dkfd_debug.c449 int xcc_id, r = kfd_dbg_get_dev_watch_id(pdd, watch_id); in kfd_dbg_trap_set_dev_address_watch() local
464 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
472 xcc_id); in kfd_dbg_trap_set_dev_address_watch()