Searched refs:wrm_reg (Results 1 – 5 of 5) sorted by relevance
922 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()923 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()924 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()930 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()931 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()932 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()933 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v11_0_misc_op()
646 op_input.wrm_reg.reg0 = reg0; in amdgpu_mes_reg_write_reg_wait()647 op_input.wrm_reg.reg1 = reg1; in amdgpu_mes_reg_write_reg_wait()648 op_input.wrm_reg.ref = ref; in amdgpu_mes_reg_write_reg_wait()649 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_write_reg_wait()
608 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_1_misc_op()609 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_1_misc_op()611 mes_v12_1_get_rrmt(input->wrm_reg.reg0, in mes_v12_1_misc_op()619 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_1_misc_op()620 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_1_misc_op()621 mes_v12_1_get_rrmt(input->wrm_reg.reg0, in mes_v12_1_misc_op()625 mes_v12_1_get_rrmt(input->wrm_reg.reg1, in mes_v12_1_misc_op()
873 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_0_misc_op()874 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_0_misc_op()875 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v12_0_misc_op()881 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_0_misc_op()882 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_0_misc_op()883 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v12_0_misc_op()884 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v12_0_misc_op()
391 } wrm_reg; member