Searched refs:wrm_reg (Results 1 – 4 of 4) sorted by relevance
507 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_0_misc_op()508 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_0_misc_op()509 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v12_0_misc_op()515 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_0_misc_op()516 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_0_misc_op()517 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v12_0_misc_op()518 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v12_0_misc_op()
621 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()622 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()623 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()629 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()630 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()631 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()632 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v11_0_misc_op()
972 op_input.wrm_reg.reg0 = reg0; in amdgpu_mes_reg_write_reg_wait()973 op_input.wrm_reg.reg1 = reg1; in amdgpu_mes_reg_write_reg_wait()974 op_input.wrm_reg.ref = ref; in amdgpu_mes_reg_write_reg_wait()975 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_write_reg_wait()998 op_input.wrm_reg.reg0 = reg; in amdgpu_mes_reg_wait()999 op_input.wrm_reg.ref = val; in amdgpu_mes_reg_wait()1000 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_wait()
334 } wrm_reg; member