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Searched refs:writeq (Results 1 – 25 of 178) sorted by relevance

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/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_rx.c21 writeq(data, base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_enable_multicast_rx()
31 writeq(data, base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_disable_multicast_rx()
43 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_enable_mac_rx_filter()
55 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_disable_mac_rx_filter()
64 writeq(dmac, base + MLXBF_GIGE_RX_MAC_FILTER + in mlxbf_gige_set_mac_rx_filter()
87 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_enable_promisc()
90 writeq(0, base + MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_START); in mlxbf_gige_enable_promisc()
94 writeq(end_mac, base + MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_END); in mlxbf_gige_enable_promisc()
105 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_disable_promisc()
154 writeq(priv->rx_wqe_base_dma, priv->base + MLXBF_GIGE_RX_WQ_BASE); in mlxbf_gige_rx_init()
[all …]
H A Dmlxbf_gige_tx.c31 writeq(priv->tx_wqe_base_dma, priv->base + MLXBF_GIGE_TX_WQ_BASE); in mlxbf_gige_tx_init()
43 writeq(priv->tx_cc_dma, priv->base + MLXBF_GIGE_TX_CI_UPDATE_ADDRESS); in mlxbf_gige_tx_init()
45 writeq(ilog2(priv->tx_q_entries), in mlxbf_gige_tx_init()
88 writeq(0, priv->base + MLXBF_GIGE_TX_WQ_BASE); in mlxbf_gige_tx_deinit()
89 writeq(0, priv->base + MLXBF_GIGE_TX_CI_UPDATE_ADDRESS); in mlxbf_gige_tx_deinit()
267 writeq(priv->tx_pi, priv->base + MLXBF_GIGE_TX_PRODUCER_INDEX); in mlxbf_gige_start_xmit()
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dptp.c134 writeq(500000000, ptp->reg_base + PTP_PPS_THRESH_HI); in ptp_reset_thresh()
258 writeq(timestamp, ptp->reg_base + PTP_NANO_TIMESTAMP); in ptp_atomic_update()
259 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_update()
260 writeq(timestamp / NSEC_PER_SEC, in ptp_atomic_update()
265 writeq(nxt_rollover_set, ptp->reg_base + PTP_NXT_ROLLOVER_SET); in ptp_atomic_update()
266 writeq(curr_rollover_set, ptp->reg_base + PTP_CURR_ROLLOVER_SET); in ptp_atomic_update()
272 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_update()
301 writeq(delta, ptp->reg_base + PTP_NANO_TIMESTAMP); in ptp_atomic_adjtime()
302 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_adjtime()
308 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_adjtime()
[all …]
/linux/drivers/cache/
H A Dstarfive_starlink_cache.c49 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr), in starlink_cache_dma_cache_wback()
51 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size), in starlink_cache_dma_cache_wback()
55 writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK, in starlink_cache_dma_cache_wback()
64 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr), in starlink_cache_dma_cache_invalidate()
66 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size), in starlink_cache_dma_cache_invalidate()
70 writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK, in starlink_cache_dma_cache_invalidate()
79 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr), in starlink_cache_dma_cache_wback_inv()
81 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size), in starlink_cache_dma_cache_wback_inv()
85 writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK, in starlink_cache_dma_cache_wback_inv()
/linux/drivers/infiniband/hw/hfi1/
H A Dpio_copy.c38 writeq(pbc, dest); in pio_copy()
51 writeq(*(u64 *)from, dest); in pio_copy()
67 writeq(*(u64 *)from, dest); in pio_copy()
86 writeq(*(u64 *)from, dest); in pio_copy()
97 writeq(*(u64 *)from, dest); in pio_copy()
110 writeq(val.val64, dest); in pio_copy()
118 writeq(0, dest); in pio_copy()
224 writeq(temp, dest); in merge_write8()
233 writeq(carry.val64, dest); in carry8_write8()
245 writeq(pbuf->carry.val64, dest); in carry_write8()
[all …]
/linux/drivers/fpga/
H A Ddfl-fme-error.c73 writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK); in pcie0_errors_store()
77 writeq(v, base + PCIE0_ERROR); in pcie0_errors_store()
81 writeq(0ULL, base + PCIE0_ERROR_MASK); in pcie0_errors_store()
118 writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK); in pcie1_errors_store()
122 writeq(v, base + PCIE1_ERROR); in pcie1_errors_store()
126 writeq(0ULL, base + PCIE1_ERROR_MASK); in pcie1_errors_store()
196 writeq(v, base + RAS_ERROR_INJECT); in inject_errors_store()
234 writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK); in fme_errors_store()
238 writeq(v, base + FME_ERROR); in fme_errors_store()
243 writeq(dfl_feature_revisio in fme_errors_store()
[all...]
H A Ddfl-fme-mgr.c102 writeq(pr_error, fme_pr + FME_PR_ERR); in fme_mgr_pr_error_handle()
125 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
136 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
160 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
178 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write()
211 writeq(pr_data, fme_pr + FME_PR_DATA); in fme_mgr_write()
230 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_complete()
/linux/drivers/gpio/
H A Dgpio-mlxbf.c114 writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD); in mlxbf_gpio_resume()
115 writeq(gs->csave_regs.pad_control[0], in mlxbf_gpio_resume()
117 writeq(gs->csave_regs.pad_control[1], in mlxbf_gpio_resume()
119 writeq(gs->csave_regs.pad_control[2], in mlxbf_gpio_resume()
121 writeq(gs->csave_regs.pad_control[3], in mlxbf_gpio_resume()
123 writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I); in mlxbf_gpio_resume()
124 writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O); in mlxbf_gpio_resume()
H A Dgpio-thunderx.c113 writeq(txgpio->line_entries[line].fil_bits, in thunderx_gpio_dir_in()
129 writeq(BIT_ULL(bank_bit), reg); in thunderx_gpio_set()
151 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_dir_out()
239 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_set_config()
283 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); in thunderx_gpio_set_multiple()
284 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); in thunderx_gpio_set_multiple()
293 writeq(GPIO_INTR_INTR, in thunderx_gpio_irq_ack()
302 writeq(GPIO_INTR_ENA_W1C, in thunderx_gpio_irq_mask()
311 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, in thunderx_gpio_irq_mask_ack()
320 writeq(GPIO_INTR_ENA_W1S, in thunderx_gpio_irq_unmask()
[all …]
/linux/drivers/mmc/host/
H A Dcavium.c212 writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); in do_switch()
215 writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); in do_switch()
247 writeq(timeout, slot->host->base + MIO_EMM_WDOG(slot->host)); in set_wdog()
267 writeq(wdog, slot->host->base + MIO_EMM_WDOG(host)); in cvm_mmc_reset_bus()
286 writeq(slot->cached_rca, host->base + MIO_EMM_RCA(host)); in cvm_mmc_switch_to()
293 writeq(emm_sample, host->base + MIO_EMM_SAMPLE(host)); in cvm_mmc_switch_to()
307 writeq((0x10000 | (dbuf << 6)), host->base + MIO_EMM_BUF_IDX(host)); in do_read()
396 writeq(BIT_ULL(16), host->dma_base + MIO_EMM_DMA_FIFO_CFG(host)); in finish_dma_sg()
432 writeq(emm_dma, host->base + MIO_EMM_DMA(host)); in cleanup_dma()
449 writeq(emm_int, host->base + MIO_EMM_INT(host)); in cvm_mmc_interrupt()
[all …]
H A Dcavium-thunderx.c33 writeq(val, host->base + MIO_EMM_INT(host)); in thunder_mmc_int_enable()
34 writeq(val, host->base + MIO_EMM_INT_EN_SET(host)); in thunder_mmc_int_enable()
123 writeq(127, host->base + MIO_EMM_INT_EN(host)); in thunder_mmc_probe()
124 writeq(3, host->base + MIO_EMM_DMA_INT_ENA_W1C(host)); in thunder_mmc_probe()
126 writeq(BIT_ULL(16), host->base + MIO_EMM_DMA_FIFO_CFG(host)); in thunder_mmc_probe()
183 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in thunder_mmc_remove()
/linux/sound/core/seq/oss/
H A Dseq_oss_ioctl.c84 if (! is_write_mode(dp->file_mode) || dp->writeq == NULL) in snd_seq_oss_ioctl()
86 while (snd_seq_oss_writeq_sync(dp->writeq)) in snd_seq_oss_ioctl()
107 if (! is_write_mode(dp->file_mode) || dp->writeq == NULL) in snd_seq_oss_ioctl()
109 return put_user(snd_seq_oss_writeq_get_free_size(dp->writeq), p) ? -EFAULT : 0; in snd_seq_oss_ioctl()
154 if (val >= dp->writeq->maxlen) in snd_seq_oss_ioctl()
155 val = dp->writeq->maxlen - 1; in snd_seq_oss_ioctl()
156 snd_seq_oss_writeq_set_output(dp->writeq, val); in snd_seq_oss_ioctl()
H A Dseq_oss_init.c235 dp->writeq = snd_seq_oss_writeq_new(dp, maxqlen); in snd_seq_oss_open()
236 if (!dp->writeq) { in snd_seq_oss_open()
388 snd_seq_oss_writeq_delete(dp->writeq); in free_devinfo()
441 if (dp->writeq) in snd_seq_oss_reset()
442 snd_seq_oss_writeq_clear(dp->writeq); in snd_seq_oss_reset()
/linux/drivers/mailbox/
H A Dqcom-cpucp-mbox.c65 writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); in qcom_cpucp_mbox_irq_fn()
80 writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); in qcom_cpucp_mbox_startup()
93 writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); in qcom_cpucp_mbox_shutdown()
132 writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); in qcom_cpucp_mbox_probe()
133 writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); in qcom_cpucp_mbox_probe()
134 writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP); in qcom_cpucp_mbox_probe()
145 writeq(APSS_CPUCP_RX_MBOX_CMD_MASK, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP); in qcom_cpucp_mbox_probe()
/linux/drivers/watchdog/
H A Dmarvell_gti_wdt.c90 writeq(GTI_CWD_INT_PENDING_STATUS(priv->wdt_timer_idx), in gti_wdt_interrupt()
102 writeq(GTI_CWD_POKE_VAL, in gti_wdt_ping()
119 writeq(GTI_CWD_INT_PENDING_STATUS(priv->wdt_timer_idx), in gti_wdt_start()
123 writeq(GTI_CWD_INT_ENA_SET_VAL(priv->wdt_timer_idx), in gti_wdt_start()
129 writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx)); in gti_wdt_start()
140 writeq(GTI_CWD_INT_ENA_CLR_VAL(priv->wdt_timer_idx), in gti_wdt_stop()
146 writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx)); in gti_wdt_stop()
182 writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx)); in gti_wdt_settimeout()
195 writeq(GTI_CWD_INT_ENA_CLR_VAL(priv->wdt_timer_idx), in gti_wdt_set_pretimeout()
/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_mailbox.c80 writeq(OCTEON_PFVFERR, in octeon_mbox_read()
115 writeq(OCTEON_PFVFACK, mbox->mbox_read_reg); in octeon_mbox_read()
172 writeq(mbox_cmd->msg.u64, mbox->mbox_write_reg); in octeon_mbox_write()
184 writeq(mbox_cmd->data[i], mbox->mbox_write_reg); in octeon_mbox_write()
193 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_write()
306 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
316 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
325 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
341 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
371 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_cancel()
/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf_mbox.c78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1)); in otx_cpt_send_msg_to_vf()
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0)); in otx_cpt_send_msg_to_vf()
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0)); in otx_cpt_clear_mbox_intr()
120 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf)); in otx_cpt_cfg_qlen_for_vf()
132 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf)); in otx_cpt_cfg_vq_priority()
162 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(q)); in otx_cpt_bind_vq_to_grp()
H A Dotx_cptvf_main.c351 writeq(vqx_ctl.u, cptvf->reg_base + OTX_CPT_VQX_CTL(0)); in cptvf_write_vq_ctl()
360 writeq(vqx_dbell.u, cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); in otx_cptvf_write_vq_doorbell()
369 writeq(vqx_inprg.u, cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); in cptvf_write_vq_inprog()
378 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_numwait()
395 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_timewait()
414 writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0)); in cptvf_enable_swerr_interrupts()
424 writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0)); in cptvf_enable_mbox_interrupts()
434 writeq(vqx_done_ena.u, cptvf->reg_base + OTX_CPT_VQX_DONE_ENA_W1S(0)); in cptvf_enable_done_interrupts()
444 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_dovf_intr()
454 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_irde_intr()
[all …]
/linux/drivers/spi/
H A Dspi-cavium.c66 writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p)); in octeon_spi_do_transfer()
78 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
85 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
102 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
113 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
/linux/drivers/edac/
H A Dthunderx_edac.c275 writeq(val, pdata->regs + _reg); \
309 writeq(val, lmc->regs + LMC_INT_W1S); in thunderx_lmc_inject_int_write()
345 writeq(lmc->mask0, lmc->regs + LMC_CHAR_MASK0); in inject_ecc_fn()
346 writeq(lmc->mask2, lmc->regs + LMC_CHAR_MASK2); in inject_ecc_fn()
347 writeq(lmc->parity_test, lmc->regs + LMC_ECC_PARITY_TEST); in inject_ecc_fn()
547 writeq(0, lmc->regs + LMC_CHAR_MASK0); in thunderx_lmc_err_isr()
548 writeq(0, lmc->regs + LMC_CHAR_MASK2); in thunderx_lmc_err_isr()
549 writeq(0x2, lmc->regs + LMC_ECC_PARITY_TEST); in thunderx_lmc_err_isr()
562 writeq(ctx->reg_int, lmc->regs + LMC_INT); in thunderx_lmc_err_isr()
772 writeq(lmc_int, lmc->regs + LMC_INT); in thunderx_lmc_probe()
[all …]
/linux/drivers/char/hw_random/
H A Dcavium-rng.c42 writeq(THUNDERX_RNM_RNG_EN | THUNDERX_RNM_ENT_EN, in cavium_rng_probe()
51 writeq(0, rng->control_status); in cavium_rng_probe()
72 writeq(0, rng->control_status); in cavium_rng_remove()
/linux/drivers/misc/ocxl/
H A Dmmio.c100 writeq(val, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_write64()
163 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_set64()
226 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_clear64()
230 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_clear64()
/linux/drivers/perf/
H A Dstarfive_starlink_pmu.c169 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_CYCLE_COUNTER); in starlink_pmu_set_event_period()
171 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_EVENT_COUNTER + in starlink_pmu_set_event_period()
200 writeq(event->hw.config, starlink_pmu->pmu_base + in starlink_pmu_counter_start()
206 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_INTERRUPT_ENABLE); in starlink_pmu_counter_start()
208 writeq(STARLINK_PMU_GLOBAL_ENABLE, starlink_pmu->pmu_base + in starlink_pmu_counter_start()
221 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_CONTROL); in starlink_pmu_counter_stop()
229 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_INTERRUPT_ENABLE); in starlink_pmu_counter_stop()
417 writeq(BIT_ULL(idx), starlink_pmu->pmu_base + in starlink_pmu_handle_irq()
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_ctrl_mbox.c103 writeq(OCTEP_CTRL_MBOX_STATUS_INIT, in octep_ctrl_mbox_init()
121 writeq(mbox->version, OCTEP_CTRL_MBOX_INFO_HOST_VERSION(mbox->barmem)); in octep_ctrl_mbox_init()
124 writeq(OCTEP_CTRL_MBOX_STATUS_READY, in octep_ctrl_mbox_init()
267 writeq(0, OCTEP_CTRL_MBOX_INFO_HOST_VERSION(mbox->barmem)); in octep_ctrl_mbox_uninit()
268 writeq(OCTEP_CTRL_MBOX_STATUS_INVALID, in octep_ctrl_mbox_uninit()
/linux/arch/alpha/include/asm/
H A Dio.h166 REMAP2(u64, writeq, volatile) in REMAP1()
252 extern void writeq(u64 b, volatile void __iomem *addr);
260 #define writeq writeq macro
500 IO_CONCAT(__IO_PREFIX,writeq)(b, addr); in __raw_writeq()
527 extern inline void writeq(u64 b, volatile void __iomem *addr) in writeq() function
588 #define writeq_relaxed writeq

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