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Searched refs:writel_bits_relaxed (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c105 writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_g12a_osd1_matrix()
149 writel_bits_relaxed(3 << 30, m[21] << 30, in meson_viu_set_osd_matrix()
151 writel_bits_relaxed(7 << 16, m[22] << 16, in meson_viu_set_osd_matrix()
155 writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_osd_matrix()
157 writel_bits_relaxed(BIT(1), 0, in meson_viu_set_osd_matrix()
168 writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0, in meson_viu_set_osd_matrix()
170 writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0, in meson_viu_set_osd_matrix()
221 writel_bits_relaxed(0x7 << 29, 7 << 29, in meson_viu_set_osd_lut()
224 writel_bits_relaxed(0x7 << 29, 0, in meson_viu_set_osd_lut()
248 writel_bits_relaxed(7 << 27, 7 << 27, in meson_viu_set_osd_lut()
[all …]
H A Dmeson_vpp.c97 writel_bits_relaxed(0xff << 16, 0xff << 16, in meson_vpp_init()
113 writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f, in meson_vpp_init()
120 writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, in meson_vpp_init()
124 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0, in meson_vpp_init()
128 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | in meson_vpp_init()
H A Dmeson_rdma.c65 writel_bits_relaxed(RDMA_ACCESS_RW_FLAG_CHAN1 | in meson_rdma_setup()
73 writel_bits_relaxed(RDMA_IRQ_CLEAR_CHAN1, in meson_rdma_stop()
78 writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, in meson_rdma_stop()
129 writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, in meson_rdma_flush()
H A Dmeson_osd_afbcd.c112 writel_bits_relaxed(OSD1_AFBCD_DEC_ENABLE, 0, in meson_gxm_afbcd_disable()
301 writel_bits_relaxed(MALI_AFBCD_MANUAL_RESET, MALI_AFBCD_MANUAL_RESET, in meson_g12a_afbcd_init()
335 writel_bits_relaxed(VPU_MAFBC_S0_ENABLE, 0, in meson_g12a_afbcd_disable()
H A Dmeson_registers.h14 #define writel_bits_relaxed(mask, val, addr) \ macro