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Searched refs:writel (Results 1 – 25 of 1537) sorted by relevance

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/linux/arch/arc/plat-hsdk/
H A Dplatform.c209 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
210 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
211 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
212 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
213 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
215 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
216 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
217 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
218 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
219 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
[all …]
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_20nm.c15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
22 writel(DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8, in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
30 writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), in dsi_20nm_dphy_set_timing()
32 writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), in dsi_20nm_dphy_set_timing()
34 writel(DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | in dsi_20nm_dphy_set_timing()
[all …]
H A Ddsi_phy_7nm.c245 writel(config->ssc_stepsize & 0xff, in dsi_pll_ssc_commit()
247 writel(config->ssc_stepsize >> 8, in dsi_pll_ssc_commit()
249 writel(config->ssc_div_per & 0xff, in dsi_pll_ssc_commit()
251 writel(config->ssc_div_per >> 8, in dsi_pll_ssc_commit()
253 writel(config->ssc_adj_per & 0xff, in dsi_pll_ssc_commit()
255 writel(config->ssc_adj_per >> 8, in dsi_pll_ssc_commit()
257 writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0), in dsi_pll_ssc_commit()
294 writel(analog_controls_five_1, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1); in dsi_pll_config_hzindep_reg()
295 writel(vco_config_1, base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1); in dsi_pll_config_hzindep_reg()
296 writel(0x01, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE); in dsi_pll_config_hzindep_reg()
[all …]
/linux/drivers/video/fbdev/via/
H A Daccel.c34 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
91 writel(tmp, engine + 0x08); in hw_bitblt_1()
100 writel(tmp, engine + 0x0C); in hw_bitblt_1()
108 writel(tmp, engine + 0x10); in hw_bitblt_1()
111 writel(fg_color, engine + 0x18); in hw_bitblt_1()
114 writel(bg_color, engine + 0x1C); in hw_bitblt_1()
124 writel(tmp, engine + 0x30); in hw_bitblt_1()
133 writel(tmp, engine + 0x34); in hw_bitblt_1()
145 writel(tmp, engine + 0x38); in hw_bitblt_1()
158 writel(ge_cmd, engine); in hw_bitblt_1()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Despi.c56 writel(V_WRITE_DATA(wr_data) | in tricn_write()
62 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
83 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); in tricn_init()
102 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, in tricn_init()
120 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_enable()
121 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
127 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_clear()
128 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear()
135 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_disable()
136 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
[all …]
H A Dtp.c32 writel(val, ap->regs + A_TP_IN_CONFIG); in tp_init()
33 writel(F_TP_OUT_CSPI_CPL | in tp_init()
37 writel(V_IP_TTL(64) | in tp_init()
47 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | in tp_init()
78 writel(0xffffffff, in t1_tp_intr_enable()
80 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_enable()
86 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); in t1_tp_intr_enable()
87 writel(tp_intr | F_PL_INTR_TP, in t1_tp_intr_enable()
99 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); in t1_tp_intr_disable()
100 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_disable()
[all …]
/linux/drivers/ata/
H A Dahci_qoriq.c134 writel(px_cmd, port_mmio + PORT_CMD); in ahci_qoriq_hardreset()
138 writel(px_is, port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset()
174 writel(SATA_ECC_DISABLE, qpriv->ecc_addr); in ahci_qoriq_phy_init()
175 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
176 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
177 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
178 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
179 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
180 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); in ahci_qoriq_phy_init()
182 writel(AHCI_PORT_AXICC_CFG, in ahci_qoriq_phy_init()
[all …]
/linux/drivers/scsi/bfa/
H A Dbfa_ioc_ct.c66 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
68 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
69 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock()
88 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
97 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
99 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
117 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
121 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_unlock()
131 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
132 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
[all …]
H A Dbfa_ioc_cb.c114 writel(~0U, ioc->ioc_regs.err_set); in bfa_ioc_cb_notify_fail()
227 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_start()
228 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); in bfa_ioc_cb_sync_start()
248 writel(1, ioc->ioc_regs.ioc_sem_reg); in bfa_ioc_cb_ownership_reset()
260 writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_join()
269 writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_leave()
278 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), in bfa_ioc_cb_set_cur_ioc_fwstate()
295 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), in bfa_ioc_cb_set_alt_ioc_fwstate()
371 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_cb_pll_init()
374 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_cb_pll_init()
[all …]
/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_ioc_ct.c131 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
133 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock()
157 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
182 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
191 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
192 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
419 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
429 writel(1, ioc->ioc_regs.lpu_read_stat); in bfa_ioc_ct2_lpu_read_stat()
452 writel(r32 & __MSIX_VT_OFST_, in bfa_nw_ioc_ct2_poweron()
457 writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) | in bfa_nw_ioc_ct2_poweron()
[all …]
/linux/sound/soc/pxa/
H A Dpxa2xx-i2s.c103 writel(0, i2s_reg_base + SACR0); in pxa2xx_i2s_startup()
175 writel(0, i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
177 writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
179 writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
180 writel(readl(i2s_reg_base + SACR1) | (pxa_i2s.fmt), i2s_reg_base + SACR1); in pxa2xx_i2s_hw_params()
183 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_TFS), i2s_reg_base + SAIMR); in pxa2xx_i2s_hw_params()
185 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_RFS), i2s_reg_base + SAIMR); in pxa2xx_i2s_hw_params()
189 writel(0x48, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
192 writel(0x34, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
195 writel(0x24, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
[all …]
/linux/sound/soc/ux500/
H A Dux500_msp_i2s.c138 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
166 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
205 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
223 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
255 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
262 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
292 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? in configure_multichannel()
295 writel(mcfg->tx_channel_0_enable, in configure_multichannel()
297 writel(mcfg->tx_channel_1_enable, in configure_multichannel()
[all …]
/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_mac.c22 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_mac_hw_stop()
23 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0); in spl2sw_mac_hw_stop()
28 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_stop()
34 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_stop()
45 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_start()
50 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_start()
60 writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8), in spl2sw_mac_addr_add()
62 writel((mac->mac_addr[2] << 0) + (mac->mac_addr[3] << 8) + in spl2sw_mac_addr_add()
69 writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0); in spl2sw_mac_addr_add()
95 writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8), in spl2sw_mac_addr_del()
[all …]
/linux/drivers/video/fbdev/geode/
H A Ddisplay_gx1.c86 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); in gx1_set_mode()
93 writel(tcfg, par->dc_regs + DC_TIMING_CFG); in gx1_set_mode()
100 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
110 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
131 writel(0, par->dc_regs + DC_FB_ST_OFFSET); in gx1_set_mode()
134 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA); in gx1_set_mode()
135 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, in gx1_set_mode()
162 writel(val, par->dc_regs + DC_H_TIMING_1); in gx1_set_mode()
164 writel(val, par->dc_regs + DC_H_TIMING_2); in gx1_set_mode()
[all …]
/linux/arch/m68k/coldfire/
H A Dm53xx.c317 writel(0x77777777, MCF_SCM_MPR); in scm_init()
321 writel(0, MCF_SCM_PACRA); in scm_init()
322 writel(0, MCF_SCM_PACRB); in scm_init()
323 writel(0, MCF_SCM_PACRC); in scm_init()
324 writel(0, MCF_SCM_PACRD); in scm_init()
325 writel(0, MCF_SCM_PACRE); in scm_init()
326 writel(0, MCF_SCM_PACRF); in scm_init()
329 writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR); in scm_init()
338 writel(0x10080000, MCF_FBCS1_CSAR); in fbcs_init()
340 writel(0x002A3780, MCF_FBCS1_CSCR); in fbcs_init()
[all …]
/linux/drivers/net/hippi/
H A Drrunner.c188 writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP, in rr_init_one()
231 writel(HALT_NIC, &rr->regs->HostCtrl); in rr_remove_one()
272 writel(*(u32*)(cmd), &regs->CmdRing[idx]); in rr_issue_cmd()
300 writel(0x01000000, &regs->TX_state); in rr_reset()
301 writel(0xff800000, &regs->RX_state); in rr_reset()
302 writel(0, &regs->AssistState); in rr_reset()
303 writel(CLEAR_INTA, &regs->LocalCtrl); in rr_reset()
304 writel(0x01, &regs->BrkPt); in rr_reset()
305 writel(0, &regs->Timer); in rr_reset()
306 writel(0, &regs->TimerRef); in rr_reset()
[all …]
/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-hw-s5p.c21 writel(1, regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
32 writel(S5P_POWER_ON, regs + S5P_JPGCLKCON); in s5p_jpeg_poweron()
48 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
62 writel(reg, regs + S5P_JPGMOD); in s5p_jpeg_proc_mode()
77 writel(reg, regs + S5P_JPGMOD); in s5p_jpeg_subsampling_mode()
92 writel(reg, regs + S5P_JPGDRI_U); in s5p_jpeg_dri()
97 writel(reg, regs + S5P_JPGDRI_L); in s5p_jpeg_dri()
107 writel(reg, regs + S5P_JPG_QTBL); in s5p_jpeg_qtbl()
118 writel(reg, regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_ac()
129 writel(reg, regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_dc()
[all …]
/linux/sound/soc/amd/ps/
H A Dps-common.c32 writel(ACP63_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL); in acp63_power_on()
42 writel(1, acp_base + ACP_SOFT_RESET); in acp63_reset()
50 writel(0, acp_base + ACP_SOFT_RESET); in acp63_reset()
57 writel(1, acp_base + ACP_EXTERNAL_INTR_ENB); in acp63_enable_interrupts()
58 writel(ACP_ERROR_IRQ, acp_base + ACP_EXTERNAL_INTR_CNTL); in acp63_enable_interrupts()
63 writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base + ACP_EXTERNAL_INTR_STAT); in acp63_disable_interrupts()
64 writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL); in acp63_disable_interrupts()
65 writel(0, acp_base + ACP_EXTERNAL_INTR_ENB); in acp63_disable_interrupts()
77 writel(0x01, acp_base + ACP_CONTROL); in acp63_init()
84 writel(0, acp_base + ACP_ZSC_DSP_CTRL); in acp63_init()
[all …]
/linux/drivers/input/touchscreen/
H A Dmxs-lradc-ts.c100 writel(LRADC_CTRL4_LRADCSELECT_MASK(vch), in mxs_lradc_map_ts_channel()
102 writel(LRADC_CTRL4_LRADCSELECT(vch, ch), in mxs_lradc_map_ts_channel()
116 writel(LRADC_CH_ACCUMULATE | in mxs_lradc_setup_ts_channel()
124 writel(LRADC_CH_VALUE_MASK, in mxs_lradc_setup_ts_channel()
135 writel(LRADC_DELAY_TRIGGER(1 << ch) | LRADC_DELAY_TRIGGER_DELAYS(0) | in mxs_lradc_setup_ts_channel()
140 writel(LRADC_CTRL1_LRADC_IRQ(ch), in mxs_lradc_setup_ts_channel()
149 writel(LRADC_DELAY_TRIGGER(0) | LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | in mxs_lradc_setup_ts_channel()
175 writel(reg, ts->base + LRADC_CH(ch1)); in mxs_lradc_setup_ts_pressure()
176 writel(reg, ts->base + LRADC_CH(ch2)); in mxs_lradc_setup_ts_pressure()
182 writel(LRADC_CH_VALUE_MASK, in mxs_lradc_setup_ts_pressure()
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-fhctl.c73 writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
74 writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
75 writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
82 writel(r, regs->reg_cfg); in fhctl_set_ssc_regs()
87 writel(r, regs->reg_cfg); in fhctl_set_ssc_regs()
89 writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org, in fhctl_set_ssc_regs()
97 writel(updnlmt_val, regs->reg_updnlmt); in fhctl_set_ssc_regs()
98 writel(readl(regs->reg_hp_en) | BIT(data->fh_id), in fhctl_set_ssc_regs()
101 writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg); in fhctl_set_ssc_regs()
103 writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg); in fhctl_set_ssc_regs()
[all …]
/linux/arch/arm/plat-orion/
H A Dpcie.c89 writel(stat, base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr()
105 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
115 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
135 writel(0, base + PCIE_BAR_CTRL_OFF(i)); in orion_pcie_setup_wins()
136 writel(0, base + PCIE_BAR_LO_OFF(i)); in orion_pcie_setup_wins()
137 writel(0, base + PCIE_BAR_HI_OFF(i)); in orion_pcie_setup_wins()
141 writel(0, base + PCIE_WIN04_CTRL_OFF(i)); in orion_pcie_setup_wins()
142 writel(0, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins()
143 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); in orion_pcie_setup_wins()
146 writel(0, base + PCIE_WIN5_CTRL_OFF); in orion_pcie_setup_wins()
[all …]
H A Dtime.c87 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_next_event()
91 writel(u, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
96 writel(delta, timer_base + TIMER1_VAL_OFF); in orion_clkevt_next_event()
103 writel(u, timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
119 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); in orion_clkevt_shutdown()
123 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_shutdown()
126 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_shutdown()
141 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); in orion_clkevt_set_periodic()
142 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); in orion_clkevt_set_periodic()
146 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_set_periodic()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
93 writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
95 writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
97 writel((m[11] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
100 writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
102 writel(m[20] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
115 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_osd_matrix()
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_dma.c38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
62 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
66 writel(upper_32_bits(dma_tx), in sxgbe_dma_channel_init()
68 writel(lower_32_bits(dma_tx), in sxgbe_dma_channel_init()
71 writel(upper_32_bits(dma_rx), in sxgbe_dma_channel_init()
73 writel(lower_32_bits(dma_rx), in sxgbe_dma_channel_init()
81 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init()
85 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init()
[all …]
/linux/drivers/gpu/ipu-v3/
H A Dipu-dp.c93 writel(reg, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha()
97 writel(reg | ((u32) alpha << 24), in ipu_dp_set_global_alpha()
101 writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha()
104 writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha()
120 writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS); in ipu_dp_set_window_pos()
141 writel(reg, flow->base + DP_COM_CONF); in ipu_dp_csc_init()
146 writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0); in ipu_dp_csc_init()
147 writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1); in ipu_dp_csc_init()
148 writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2); in ipu_dp_csc_init()
149 writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3); in ipu_dp_csc_init()
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