Home
last modified time | relevance | path

Searched refs:write_sysreg_el1 (Results 1 – 14 of 14) sorted by relevance

/linux/arch/arm64/kvm/hyp/vhe/
H A Dsysreg-sr.c95 write_sysreg_el1(__vcpu_sys_reg(vcpu, MAIR_EL2), SYS_MAIR); in __sysreg_restore_vel2_state()
96 write_sysreg_el1(__vcpu_sys_reg(vcpu, VBAR_EL2), SYS_VBAR); in __sysreg_restore_vel2_state()
97 write_sysreg_el1(__vcpu_sys_reg(vcpu, CONTEXTIDR_EL2), SYS_CONTEXTIDR); in __sysreg_restore_vel2_state()
98 write_sysreg_el1(__vcpu_sys_reg(vcpu, AMAIR_EL2), SYS_AMAIR); in __sysreg_restore_vel2_state()
105 write_sysreg_el1(__vcpu_sys_reg(vcpu, SCTLR_EL2), SYS_SCTLR); in __sysreg_restore_vel2_state()
106 write_sysreg_el1(__vcpu_sys_reg(vcpu, CPTR_EL2), SYS_CPACR); in __sysreg_restore_vel2_state()
107 write_sysreg_el1(__vcpu_sys_reg(vcpu, TTBR0_EL2), SYS_TTBR0); in __sysreg_restore_vel2_state()
108 write_sysreg_el1(__vcpu_sys_reg(vcpu, TTBR1_EL2), SYS_TTBR1); in __sysreg_restore_vel2_state()
109 write_sysreg_el1(__vcpu_sys_reg(vcpu, TCR_EL2), SYS_TCR); in __sysreg_restore_vel2_state()
110 write_sysreg_el1(__vcpu_sys_reg(vcpu, CNTHCTL_EL2), SYS_CNTKCTL); in __sysreg_restore_vel2_state()
[all …]
H A Dtlb.c45 write_sysreg_el1(val, SYS_TCR); in enter_vmid_context()
48 write_sysreg_el1(val, SYS_SCTLR); in enter_vmid_context()
85 write_sysreg_el1(cxt->tcr, SYS_TCR); in exit_vmid_context()
86 write_sysreg_el1(cxt->sctlr, SYS_SCTLR); in exit_vmid_context()
/linux/arch/arm64/kvm/hyp/include/hyp/
H A Dsysreg-sr.h219 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); in __sysreg_restore_el1_state()
220 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); in __sysreg_restore_el1_state()
227 write_sysreg_el1((ctxt_sys_reg(ctxt, TCR_EL1) | in __sysreg_restore_el1_state()
233 write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1), SYS_CPACR); in __sysreg_restore_el1_state()
234 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1), SYS_TTBR0); in __sysreg_restore_el1_state()
235 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1), SYS_TTBR1); in __sysreg_restore_el1_state()
237 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1), SYS_TCR2); in __sysreg_restore_el1_state()
240 write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR); in __sysreg_restore_el1_state()
241 write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0); in __sysreg_restore_el1_state()
245 write_sysreg_el1(ctxt_sys_reg(ctxt, POR_EL1), SYS_POR); in __sysreg_restore_el1_state()
[all …]
H A Dswitch.h453 write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)), SYS_ZCR); in __hyp_sve_restore_guest()
484 write_sysreg_el1(zcr_el1, SYS_ZCR); in fpsimd_lazy_switch_to_guest()
521 write_sysreg_el1(zcr_el1, SYS_ZCR); in fpsimd_lazy_switch_to_host()
632 write_sysreg_el1(val, SYS_SCTLR); in handle_tx2_tvm()
635 write_sysreg_el1(val, SYS_TTBR0); in handle_tx2_tvm()
638 write_sysreg_el1(val, SYS_TTBR1); in handle_tx2_tvm()
641 write_sysreg_el1(val, SYS_TCR); in handle_tx2_tvm()
644 write_sysreg_el1(val, SYS_ESR); in handle_tx2_tvm()
647 write_sysreg_el1(val, SYS_FAR); in handle_tx2_tvm()
650 write_sysreg_el1(val, SYS_AFSR0); in handle_tx2_tvm()
[all …]
/linux/arch/arm64/kvm/hyp/nvhe/
H A Ddebug-sr.c35 write_sysreg_el1(0, SYS_PMSCR); in __debug_save_spe()
51 write_sysreg_el1(pmscr_el1, SYS_PMSCR); in __debug_restore_spe()
57 write_sysreg_el1(new_trfcr, SYS_TRFCR); in __trace_do_switch()
109 write_sysreg_el1(0, SYS_BRBCR); in __debug_save_brbe()
118 write_sysreg_el1(brbcr_el1, SYS_BRBCR); in __debug_restore_brbe()
H A Dtlb.c88 write_sysreg_el1(val, SYS_TCR); in enter_vmid_context()
95 write_sysreg_el1(val, SYS_SCTLR); in enter_vmid_context()
140 write_sysreg_el1(cxt->sctlr, SYS_SCTLR); in exit_vmid_context()
144 write_sysreg_el1(cxt->tcr, SYS_TCR); in exit_vmid_context()
H A Dswitch.c71 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); in __activate_traps()
73 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); in __activate_traps()
93 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR); in __deactivate_traps()
96 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR); in __deactivate_traps()
H A Dsys_regs.c262 write_sysreg_el1(esr, SYS_ESR); in inject_undef64()
263 write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR); in inject_undef64()
H A Dpsci-relay.c221 write_sysreg_el1(INIT_SCTLR_EL1_MMU_OFF, SYS_SCTLR); in __kvm_host_psci_cpu_entry()
H A Dhyp-main.c57 write_sysreg_el1(sve_state->zcr_el1, SYS_ZCR); in __hyp_sve_restore_host()
/linux/arch/arm64/kvm/
H A Dat.c624 write_sysreg_el1(config->ttbr0, SYS_TTBR0); in __mmu_config_restore()
625 write_sysreg_el1(config->ttbr1, SYS_TTBR1); in __mmu_config_restore()
626 write_sysreg_el1(config->tcr, SYS_TCR); in __mmu_config_restore()
627 write_sysreg_el1(config->mair, SYS_MAIR); in __mmu_config_restore()
629 write_sysreg_el1(config->tcr2, SYS_TCR2); in __mmu_config_restore()
631 write_sysreg_el1(config->pir, SYS_PIR); in __mmu_config_restore()
632 write_sysreg_el1(config->pire0, SYS_PIRE0); in __mmu_config_restore()
635 write_sysreg_el1(config->por_el1, SYS_POR); in __mmu_config_restore()
639 write_sysreg_el1(config->sctlr, SYS_SCTLR); in __mmu_config_restore()
1389 write_sysreg_el1(vcpu_read_sys_reg(vcpu, TTBR0_EL1), SYS_TTBR0); in __kvm_at_s1e01_fast()
[all …]
H A Ddebug.c111 write_sysreg_el1(0, SYS_PMSCR); in kvm_debug_init_vhe()
H A Dsys_regs.c360 write_sysreg_el1(val, SYS_CNTKCTL); in vcpu_write_sys_reg()
/linux/arch/arm64/include/asm/
H A Dkvm_hyp.h30 #define write_sysreg_el1(v,r) write_sysreg_s(v, r##_EL12) macro
64 #define write_sysreg_el1(v,r) write_sysreg_elx(v, r, _EL1, _EL12) macro