/linux/drivers/media/usb/pvrusb2/ |
H A D | pvrusb2-debugifc.c | 50 const char *wptr; in debugifc_isolate_word() local 55 wptr = NULL; in debugifc_isolate_word() 63 wptr = buf; in debugifc_isolate_word() 68 *wstrPtr = wptr; in debugifc_isolate_word() 177 const char *wptr; in pvr2_debugifc_do1cmd() local 181 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd() 184 if (!wptr) return 0; in pvr2_debugifc_do1cmd() 186 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); in pvr2_debugifc_do1cmd() 187 if (debugifc_match_keyword(wptr,wlen,"reset")) { in pvr2_debugifc_do1cmd() 188 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd() [all …]
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/linux/drivers/media/platform/amphion/ |
H A D | vpu_rpc.c | 39 ptr1 = desc->wptr; in vpu_rpc_check_buffer_space() 43 ptr2 = desc->wptr; in vpu_rpc_check_buffer_space() 61 u32 wptr; in vpu_rpc_send_cmd_buf() local 70 wptr = desc->wptr; in vpu_rpc_send_cmd_buf() 71 data = (u32 *)(shared->cmd_mem_vir + desc->wptr - desc->start); in vpu_rpc_send_cmd_buf() 76 wptr += 4; in vpu_rpc_send_cmd_buf() 78 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf() 79 wptr = desc->start; in vpu_rpc_send_cmd_buf() 85 wptr += 4; in vpu_rpc_send_cmd_buf() 87 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf() [all …]
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H A D | vpu_malone.c | 187 u32 wptr; member 313 u32 wptr; member 370 iface->cmd_buffer_desc.buffer.wptr = phy_addr; in vpu_malone_init_rpc() 378 iface->msg_buffer_desc.buffer.wptr = in vpu_malone_init_rpc() 422 iface->eng_access_buff_desc[i].buffer.wptr = in vpu_malone_init_rpc() 445 iface->debug_buffer_desc.buffer.wptr = in vpu_malone_set_log_buf() 497 writel(buf->phys, &str_buf->wptr); in vpu_malone_config_stream_buffer() 514 desc->wptr = readl(&str_buf->wptr); in vpu_malone_get_stream_buffer_desc() 523 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr) in vpu_malone_update_wptr() argument 527 writel(wptr, &str_buf->wptr); in vpu_malone_update_wptr() [all …]
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H A D | vpu_helpers.c | 271 u32 *wptr, u32 size, void *src) in vpu_helper_copy_to_stream_buffer() argument 278 if (!stream_buffer || !wptr || !src) in vpu_helper_copy_to_stream_buffer() 284 offset = *wptr; in vpu_helper_copy_to_stream_buffer() 298 *wptr = vpu_helper_step_walk(stream_buffer, offset, size); in vpu_helper_copy_to_stream_buffer() 304 u32 *wptr, u8 val, u32 size) in vpu_helper_memset_stream_buffer() argument 311 if (!stream_buffer || !wptr) in vpu_helper_memset_stream_buffer() 317 offset = *wptr; in vpu_helper_memset_stream_buffer() 335 *wptr = offset; in vpu_helper_memset_stream_buffer() 347 if (desc.rptr > desc.wptr) in vpu_helper_get_free_space() 348 return desc.rptr - desc.wptr; in vpu_helper_get_free_space() [all …]
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H A D | vpu_dbg.c | 287 iface->cmd_desc->wptr, in vpu_dbg_core() 295 iface->msg_desc->wptr, in vpu_dbg_core() 309 u32 wptr; in vpu_dbg_fwlog() local 317 wptr = print_buf->write; in vpu_dbg_fwlog() 319 if (rptr == wptr) in vpu_dbg_fwlog() 321 else if (rptr < wptr) in vpu_dbg_fwlog() 322 length = wptr - rptr; in vpu_dbg_fwlog() 324 length = print_buf->bytes + wptr - rptr; in vpu_dbg_fwlog()
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_ih.c | 152 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; in amdgpu_ih_ring_write() local 156 ih->ring[wptr++] = cpu_to_le32(iv[i]); in amdgpu_ih_ring_write() 158 wptr <<= 2; in amdgpu_ih_ring_write() 159 wptr &= ih->ptr_mask; in amdgpu_ih_ring_write() 162 if (wptr != READ_ONCE(ih->rptr)) { in amdgpu_ih_ring_write() 164 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); in amdgpu_ih_ring_write() 167 wptr, ih->rptr); in amdgpu_ih_ring_write() 211 u32 wptr; in amdgpu_ih_process() local 216 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process() 220 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); in amdgpu_ih_process() [all …]
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H A D | amdgpu_ring_mux.c | 212 void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr) in amdgpu_ring_mux_set_wptr() argument 238 e->sw_wptr = wptr; in amdgpu_ring_mux_set_wptr() 239 e->start_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr() 242 if (ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT || mux->wptr_resubmit < wptr) { in amdgpu_ring_mux_set_wptr() 243 amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, ring, e->sw_cptr, wptr); in amdgpu_ring_mux_set_wptr() 244 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr() 247 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr() 339 amdgpu_ring_mux_set_wptr(mux, ring, ring->wptr); in amdgpu_sw_ring_set_wptr_gfx() 427 offset = ring->wptr & ring->buf_mask; in amdgpu_sw_ring_ib_mark_offset() 453 chunk->start = ring->wptr; in amdgpu_ring_mux_start_ib() [all …]
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H A D | sdma_v5_0.c | 311 ret = ring->wptr & ring->buf_mask; in sdma_v5_0_ring_init_cond_exec() 346 u64 wptr; in sdma_v5_0_ring_get_wptr() local 350 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v5_0_ring_get_wptr() 351 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v5_0_ring_get_wptr() 353 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr() 354 wptr = wptr << 32; in sdma_v5_0_ring_get_wptr() 355 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_get_wptr() 356 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); in sdma_v5_0_ring_get_wptr() 359 return wptr >> 2; in sdma_v5_0_ring_get_wptr() 387 ring->wptr << 2); in sdma_v5_0_ring_set_wptr() [all …]
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H A D | sdma_v4_4_2.c | 233 u64 wptr; in sdma_v4_4_2_ring_get_wptr() local 237 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_4_2_ring_get_wptr() 238 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v4_4_2_ring_get_wptr() 240 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); in sdma_v4_4_2_ring_get_wptr() 241 wptr = wptr << 32; in sdma_v4_4_2_ring_get_wptr() 242 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); in sdma_v4_4_2_ring_get_wptr() 244 ring->me, wptr); in sdma_v4_4_2_ring_get_wptr() 247 return wptr >> 2; in sdma_v4_4_2_ring_get_wptr() 270 lower_32_bits(ring->wptr << 2), in sdma_v4_4_2_ring_set_wptr() 271 upper_32_bits(ring->wptr << 2)); in sdma_v4_4_2_ring_set_wptr() [all …]
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H A D | sdma_v7_0.c | 152 ret = ring->wptr & ring->buf_mask; in sdma_v7_0_ring_init_cond_exec() 186 u64 wptr = 0; in sdma_v7_0_ring_get_wptr() local 190 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v7_0_ring_get_wptr() 191 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v7_0_ring_get_wptr() 194 return wptr >> 2; in sdma_v7_0_ring_get_wptr() 223 ring->wptr << 2); in sdma_v7_0_ring_set_wptr() 224 *wptr_saved = ring->wptr << 2; in sdma_v7_0_ring_set_wptr() 226 WDOORBELL64(aggregated_db_index, ring->wptr << 2); in sdma_v7_0_ring_set_wptr() 228 ring->doorbell_index, ring->wptr << 2); in sdma_v7_0_ring_set_wptr() 229 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); in sdma_v7_0_ring_set_wptr() [all …]
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H A D | sdma_v5_2.c | 151 ret = ring->wptr & ring->buf_mask; in sdma_v5_2_ring_init_cond_exec() 186 u64 wptr; in sdma_v5_2_ring_get_wptr() local 190 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v5_2_ring_get_wptr() 191 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v5_2_ring_get_wptr() 193 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_2_ring_get_wptr() 194 wptr = wptr << 32; in sdma_v5_2_ring_get_wptr() 195 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_2_ring_get_wptr() 196 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); in sdma_v5_2_ring_get_wptr() 199 return wptr >> 2; in sdma_v5_2_ring_get_wptr() 220 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr() [all …]
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H A D | vcn_v3_0.c | 367 ring->wptr = 0; in vcn_v3_0_hw_init() 380 ring->wptr = 0; in vcn_v3_0_hw_init() 1119 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start_dpg_mode() 1121 lower_32_bits(ring->wptr)); in vcn_v3_0_start_dpg_mode() 1125 fw_shared->rb.wptr = lower_32_bits(ring->wptr); in vcn_v3_0_start_dpg_mode() 1295 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start() 1297 lower_32_bits(ring->wptr)); in vcn_v3_0_start() 1298 fw_shared->rb.wptr = lower_32_bits(ring->wptr); in vcn_v3_0_start() 1305 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start() 1306 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start() [all …]
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H A D | sdma_v4_0.c | 674 u64 wptr; in sdma_v4_0_ring_get_wptr() local 678 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v4_0_ring_get_wptr() 679 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v4_0_ring_get_wptr() 681 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); in sdma_v4_0_ring_get_wptr() 682 wptr = wptr << 32; in sdma_v4_0_ring_get_wptr() 683 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); in sdma_v4_0_ring_get_wptr() 685 ring->me, wptr); in sdma_v4_0_ring_get_wptr() 688 return wptr >> 2; in sdma_v4_0_ring_get_wptr() 711 lower_32_bits(ring->wptr << 2), in sdma_v4_0_ring_set_wptr() 712 upper_32_bits(ring->wptr << 2)); in sdma_v4_0_ring_set_wptr() [all …]
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H A D | vcn_v2_0.c | 961 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start_dpg_mode() 963 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode() 1119 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start() 1121 lower_32_bits(ring->wptr)); in vcn_v2_0_start() 1126 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start() 1127 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start() 1135 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start() 1136 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start() 1279 ring->wptr = 0; in vcn_v2_0_pause_dpg_mode() 1283 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode() [all …]
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H A D | vce_v4_0.c | 109 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr() 110 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr() 116 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr() 119 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr() 122 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr() 181 adev->vce.ring[0].wptr = 0; in vce_v4_0_mmsch_start() 343 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start() 344 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start() 351 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start() 352 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start() [all …]
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H A D | sdma_v6_0.c | 151 ret = ring->wptr & ring->buf_mask; in sdma_v6_0_ring_init_cond_exec() 185 u64 wptr = 0; in sdma_v6_0_ring_get_wptr() local 189 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v6_0_ring_get_wptr() 190 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v6_0_ring_get_wptr() 193 return wptr >> 2; in sdma_v6_0_ring_get_wptr() 213 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr() 214 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr() 217 ring->wptr << 2); in sdma_v6_0_ring_set_wptr() 219 ring->doorbell_index, ring->wptr << 2); in sdma_v6_0_ring_set_wptr() 220 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); in sdma_v6_0_ring_set_wptr() [all …]
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/linux/drivers/net/ppp/ |
H A D | bsd_comp.c | 580 unsigned char *wptr; in bsd_compress() local 586 if (wptr) \ in bsd_compress() 588 *wptr++ = (unsigned char) (v); \ in bsd_compress() 591 wptr = NULL; \ in bsd_compress() 630 wptr = obuf; in bsd_compress() 639 if (wptr) in bsd_compress() 641 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress() 642 *wptr++ = PPP_CONTROL(rptr); in bsd_compress() 643 *wptr++ = 0; in bsd_compress() 644 *wptr++ = PPP_COMP; in bsd_compress() [all …]
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H A D | ppp_deflate.c | 190 unsigned char *wptr; in z_compress() local 204 wptr = obuf; in z_compress() 209 wptr[0] = PPP_ADDRESS(rptr); in z_compress() 210 wptr[1] = PPP_CONTROL(rptr); in z_compress() 211 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress() 212 wptr += PPP_HDRLEN; in z_compress() 213 put_unaligned_be16(state->seqno, wptr); in z_compress() 214 wptr += DEFLATE_OVHD; in z_compress() 216 state->strm.next_out = wptr; in z_compress()
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/linux/drivers/net/ethernet/tehuti/ |
H A D | tehuti.c | 171 f->wptr = 0; in bdx_fifo_init() 1101 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_rx_alloc_skbs() 1109 f->m.wptr += sizeof(struct rxf_desc); in bdx_rx_alloc_skbs() 1110 delta = f->m.wptr - f->m.memsz; in bdx_rx_alloc_skbs() 1112 f->m.wptr = delta; in bdx_rx_alloc_skbs() 1121 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); in bdx_rx_alloc_skbs() 1156 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_recycle_skb() 1164 f->m.wptr += sizeof(struct rxf_desc); in bdx_recycle_skb() 1165 delta = f->m.wptr - f->m.memsz; in bdx_recycle_skb() 1167 f->m.wptr = delta; in bdx_recycle_skb() [all …]
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H A D | tn40.c | 54 f->wptr = 0; in tn40_fifo_alloc() 212 rxfd = (struct tn40_rxf_desc *)(f->m.va + f->m.wptr); in tn40_set_rx_desc() 218 f->m.wptr += sizeof(struct tn40_rxf_desc); in tn40_set_rx_desc() 219 delta = f->m.wptr - f->m.memsz; in tn40_set_rx_desc() 221 f->m.wptr = delta; in tn40_set_rx_desc() 261 f->m.wptr & TN40_TXF_WPTR_WR_PTR); in tn40_rx_alloc_buffers() 263 f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR); in tn40_rx_alloc_buffers() 281 tn40_write_reg(priv, f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR); in tn40_recycle_rx_buffer() 296 f->m.wptr = tn40_read_reg(priv, f->m.reg_wptr) & TN40_TXF_WPTR_WR_PTR; in tn40_rx_receive() 297 size = f->m.wptr - f->m.rptr; in tn40_rx_receive() [all …]
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/linux/drivers/crypto/ccp/ |
H A D | tee-dev.c | 104 tee->rb_mgr.wptr = 0; in tee_init_ring() 230 (tee->rb_mgr.ring_start + tee->rb_mgr.wptr); in tee_submit_cmd() 237 if (!(tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd() 242 rptr, tee->rb_mgr.wptr); in tee_submit_cmd() 252 (tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd() 255 rptr, tee->rb_mgr.wptr, cmd->flag); in tee_submit_cmd() 278 tee->rb_mgr.wptr += sizeof(struct tee_ring_cmd); in tee_submit_cmd() 279 if (tee->rb_mgr.wptr >= tee->rb_mgr.ring_size) in tee_submit_cmd() 280 tee->rb_mgr.wptr = 0; in tee_submit_cmd() 283 iowrite32(tee->rb_mgr.wptr, tee->io_regs + tee->vdata->ring_wptr_reg); in tee_submit_cmd()
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/linux/drivers/gpu/drm/radeon/ |
H A D | radeon_ring.c | 89 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size() 130 ring->wptr_old = ring->wptr; in radeon_ring_alloc() 178 while (ring->wptr & ring->align_mask) { in radeon_ring_commit() 216 ring->wptr = ring->wptr_old; in radeon_ring_undo() 316 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup() 472 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info_show() local 478 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info_show() 480 wptr, wptr); in radeon_debugfs_ring_info_show() 494 ring->wptr, ring->wptr); in radeon_debugfs_ring_info_show()
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H A D | vce_v1_0.c | 98 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr() 100 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr() 298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start() 299 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start() 305 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start() 306 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
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/linux/drivers/video/fbdev/ |
H A D | maxinefb.c | 67 unsigned char *wptr; in maxinefb_ims332_write_register() local 69 wptr = regs + 0xa0000 + (regno << 4); in maxinefb_ims332_write_register() 71 *((volatile unsigned short *) (wptr)) = val; in maxinefb_ims332_write_register()
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/linux/drivers/gpu/drm/msm/adreno/ |
H A D | a5xx_preempt.c | 43 uint32_t wptr; in update_wptr() local 49 wptr = get_wptr(ring); in update_wptr() 52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr() 148 a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring); in a5xx_preempt_trigger() 232 a5xx_gpu->preempt[i]->wptr = 0; in a5xx_preempt_hw_init()
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