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Searched refs:wptr (Results 1 – 25 of 85) sorted by relevance

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/linux/drivers/media/platform/amphion/
H A Dvpu_rpc.c39 ptr1 = desc->wptr; in vpu_rpc_check_buffer_space()
43 ptr2 = desc->wptr; in vpu_rpc_check_buffer_space()
61 u32 wptr; in vpu_rpc_send_cmd_buf() local
70 wptr = desc->wptr; in vpu_rpc_send_cmd_buf()
71 data = (u32 *)(shared->cmd_mem_vir + desc->wptr - desc->start); in vpu_rpc_send_cmd_buf()
76 wptr += 4; in vpu_rpc_send_cmd_buf()
78 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf()
79 wptr = desc->start; in vpu_rpc_send_cmd_buf()
85 wptr += 4; in vpu_rpc_send_cmd_buf()
87 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf()
[all …]
/linux/drivers/net/ppp/
H A Dbsd_comp.c579 unsigned char *wptr; in bsd_compress() local
585 if (wptr) \ in bsd_compress()
587 *wptr++ = (unsigned char) (v); \ in bsd_compress()
590 wptr = NULL; \ in bsd_compress()
629 wptr = obuf; in bsd_compress()
638 if (wptr) in bsd_compress()
640 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress()
641 *wptr++ = PPP_CONTROL(rptr); in bsd_compress()
642 *wptr++ = 0; in bsd_compress()
643 *wptr++ = PPP_COMP; in bsd_compress()
[all …]
H A Dppp_deflate.c189 unsigned char *wptr; in z_compress() local
203 wptr = obuf; in z_compress()
208 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
209 wptr[1] = PPP_CONTROL(rptr); in z_compress()
210 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress()
211 wptr += PPP_HDRLEN; in z_compress()
212 put_unaligned_be16(state->seqno, wptr); in z_compress()
213 wptr += DEFLATE_OVHD; in z_compress()
215 state->strm.next_out = wptr; in z_compress()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Diceland_ih.c196 u32 wptr, tmp; in iceland_ih_get_wptr() local
198 wptr = le32_to_cpu(*ih->wptr_cpu); in iceland_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
207 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
209 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
212 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in iceland_ih_get_wptr()
218 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
219 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
231 return (wptr & ih->ptr_mask); in iceland_ih_get_wptr()
H A Dcz_ih.c196 u32 wptr, tmp; in cz_ih_get_wptr() local
198 wptr = le32_to_cpu(*ih->wptr_cpu); in cz_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
207 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
209 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
212 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in cz_ih_get_wptr()
219 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
220 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
232 return (wptr & ih->ptr_mask); in cz_ih_get_wptr()
H A Dtonga_ih.c198 u32 wptr, tmp; in tonga_ih_get_wptr() local
200 wptr = le32_to_cpu(*ih->wptr_cpu); in tonga_ih_get_wptr()
205 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
209 wptr = RREG32(mmIH_RB_WPTR); in tonga_ih_get_wptr()
211 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
214 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in tonga_ih_get_wptr()
222 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
223 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
235 return (wptr & ih->ptr_mask); in tonga_ih_get_wptr()
H A Dsi_ih.c114 u32 wptr, tmp; in si_ih_get_wptr() local
116 wptr = le32_to_cpu(*ih->wptr_cpu); in si_ih_get_wptr()
121 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in si_ih_get_wptr()
122 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in si_ih_get_wptr()
124 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
125 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
138 return (wptr & ih->ptr_mask); in si_ih_get_wptr()
H A Dcik_ih.c194 u32 wptr, tmp; in cik_ih_get_wptr() local
196 wptr = le32_to_cpu(*ih->wptr_cpu); in cik_ih_get_wptr()
201 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in cik_ih_get_wptr()
202 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in cik_ih_get_wptr()
208 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
209 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
222 return (wptr & ih->ptr_mask); in cik_ih_get_wptr()
H A Damdgpu_ring_mux.c213 void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr) in amdgpu_ring_mux_set_wptr() argument
239 e->sw_wptr = wptr; in amdgpu_ring_mux_set_wptr()
240 e->start_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
243 if (ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT || mux->wptr_resubmit < wptr) { in amdgpu_ring_mux_set_wptr()
244 amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, ring, e->sw_cptr, wptr); in amdgpu_ring_mux_set_wptr()
245 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
248 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
340 amdgpu_ring_mux_set_wptr(mux, ring, ring->wptr); in amdgpu_sw_ring_set_wptr_gfx()
428 offset = ring->wptr & ring->buf_mask; in amdgpu_sw_ring_ib_mark_offset()
454 chunk->start = ring->wptr; in amdgpu_ring_mux_start_ib()
[all …]
H A Dsdma_v5_2.c153 ret = ring->wptr & ring->buf_mask; in sdma_v5_2_ring_init_cond_exec()
188 u64 wptr; in sdma_v5_2_ring_get_wptr() local
192 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v5_2_ring_get_wptr()
193 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v5_2_ring_get_wptr()
195 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_2_ring_get_wptr()
196 wptr = wptr << 32; in sdma_v5_2_ring_get_wptr()
197 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_2_ring_get_wptr()
198 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); in sdma_v5_2_ring_get_wptr()
201 return wptr >> 2; in sdma_v5_2_ring_get_wptr()
222 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
[all …]
H A Damdgpu_fence.c94 af->fence_wptr_start = af->ring->wptr; in amdgpu_fence_save_fence_wptr_start()
99 af->fence_wptr_end = af->ring->wptr; in amdgpu_fence_save_fence_wptr_end()
262 drv->signalled_wptr = am_fence->wptr; in amdgpu_fence_process()
762 af->wptr = af->ring->wptr; in amdgpu_fence_save_wptr()
783 u64 wptr; in amdgpu_ring_backup_unprocessed_commands() local
788 wptr = ring->fence_drv.signalled_wptr; in amdgpu_ring_backup_unprocessed_commands()
807 amdgpu_ring_backup_unprocessed_command(ring, wptr, in amdgpu_ring_backup_unprocessed_commands()
808 fence->wptr); in amdgpu_ring_backup_unprocessed_commands()
815 wptr = fence->wptr; in amdgpu_ring_backup_unprocessed_commands()
H A Dsdma_v5_0.c313 ret = ring->wptr & ring->buf_mask; in sdma_v5_0_ring_init_cond_exec()
348 u64 wptr; in sdma_v5_0_ring_get_wptr() local
352 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v5_0_ring_get_wptr()
353 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v5_0_ring_get_wptr()
355 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr()
356 wptr = wptr << 32; in sdma_v5_0_ring_get_wptr()
357 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_get_wptr()
358 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); in sdma_v5_0_ring_get_wptr()
361 return wptr >> 2; in sdma_v5_0_ring_get_wptr()
382 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
[all …]
H A Dsdma_v6_0.c155 ret = ring->wptr & ring->buf_mask; in sdma_v6_0_ring_init_cond_exec()
189 u64 wptr = 0; in sdma_v6_0_ring_get_wptr() local
193 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v6_0_ring_get_wptr()
194 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v6_0_ring_get_wptr()
197 return wptr >> 2; in sdma_v6_0_ring_get_wptr()
217 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
218 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
221 ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
223 ring->doorbell_index, ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
224 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
[all …]
H A Damdgpu_ring.c99 ring->wptr_old = ring->wptr; in amdgpu_ring_alloc()
124 ring->wptr_old = ring->wptr; in amdgpu_ring_alloc_reemit()
142 occupied = ring->wptr & ring->buf_mask; in amdgpu_ring_insert_nop()
153 ring->wptr += count; in amdgpu_ring_insert_nop()
154 ring->wptr &= ring->ptr_mask; in amdgpu_ring_insert_nop()
198 (ring->wptr & ring->funcs->align_mask); in amdgpu_ring_commit()
220 ring->wptr = ring->wptr_old; in amdgpu_ring_undo()
364 ring->wptr = *ring->rptr_cpu_addr = 0; in amdgpu_ring_init()
594 early[2] = ring->wptr & ring->buf_mask; in amdgpu_debugfs_ring_read()
817 ring->wptr = 0; in amdgpu_ring_init_mqd()
H A Damdgpu_ring.h150 u64 wptr; member
326 u64 wptr; member
495 ring->ring[ring->wptr++ & ring->buf_mask] = v; in amdgpu_ring_write()
496 ring->wptr &= ring->ptr_mask; in amdgpu_ring_write()
505 occupied = ring->wptr & ring->buf_mask; in amdgpu_ring_write_multiple()
520 ring->wptr += count_dw; in amdgpu_ring_write_multiple()
521 ring->wptr &= ring->ptr_mask; in amdgpu_ring_write_multiple()
543 cur = (ring->wptr - 1) & ring->buf_mask; in amdgpu_ring_patch_cond_exec()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_kernel_queue.c206 uint32_t wptr, rptr; in kq_acquire_packet_buffer() local
216 wptr = kq->pending_wptr; in kq_acquire_packet_buffer()
222 pr_debug("wptr: %d\n", wptr); in kq_acquire_packet_buffer()
225 available_size = (rptr + queue_size_dwords - 1 - wptr) % in kq_acquire_packet_buffer()
236 if (wptr + packet_size_in_dwords >= queue_size_dwords) { in kq_acquire_packet_buffer()
244 while (wptr > 0) { in kq_acquire_packet_buffer()
245 queue_address[wptr] = kq->nop_packet; in kq_acquire_packet_buffer()
246 wptr = (wptr + 1) % queue_size_dwords; in kq_acquire_packet_buffer()
251 *buffer_ptr = &queue_address[wptr]; in kq_acquire_packet_buffer()
252 kq->pending_wptr = wptr + packet_size_in_dwords; in kq_acquire_packet_buffer()
/linux/drivers/net/ethernet/tehuti/
H A Dtehuti.c171 f->wptr = 0; in bdx_fifo_init()
1101 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_rx_alloc_skbs()
1109 f->m.wptr += sizeof(struct rxf_desc); in bdx_rx_alloc_skbs()
1110 delta = f->m.wptr - f->m.memsz; in bdx_rx_alloc_skbs()
1112 f->m.wptr = delta; in bdx_rx_alloc_skbs()
1121 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); in bdx_rx_alloc_skbs()
1156 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_recycle_skb()
1164 f->m.wptr += sizeof(struct rxf_desc); in bdx_recycle_skb()
1165 delta = f->m.wptr - f->m.memsz; in bdx_recycle_skb()
1167 f->m.wptr = delta; in bdx_recycle_skb()
[all …]
H A Dtn40.c54 f->wptr = 0; in tn40_fifo_alloc()
212 rxfd = (struct tn40_rxf_desc *)(f->m.va + f->m.wptr); in tn40_set_rx_desc()
218 f->m.wptr += sizeof(struct tn40_rxf_desc); in tn40_set_rx_desc()
219 delta = f->m.wptr - f->m.memsz; in tn40_set_rx_desc()
221 f->m.wptr = delta; in tn40_set_rx_desc()
261 f->m.wptr & TN40_TXF_WPTR_WR_PTR); in tn40_rx_alloc_buffers()
263 f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR); in tn40_rx_alloc_buffers()
281 tn40_write_reg(priv, f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR); in tn40_recycle_rx_buffer()
296 f->m.wptr = tn40_read_reg(priv, f->m.reg_wptr) & TN40_TXF_WPTR_WR_PTR; in tn40_rx_receive()
297 size = f->m.wptr - f->m.rptr; in tn40_rx_receive()
[all …]
/linux/drivers/crypto/ccp/
H A Dtee-dev.c128 tee->rb_mgr.wptr = 0; in tee_init_ring()
257 (tee->rb_mgr.ring_start + tee->rb_mgr.wptr); in tee_submit_cmd()
264 if (!(tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
269 rptr, tee->rb_mgr.wptr); in tee_submit_cmd()
279 (tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
282 rptr, tee->rb_mgr.wptr, cmd->flag); in tee_submit_cmd()
305 tee->rb_mgr.wptr += sizeof(struct tee_ring_cmd); in tee_submit_cmd()
306 if (tee->rb_mgr.wptr >= tee->rb_mgr.ring_size) in tee_submit_cmd()
307 tee->rb_mgr.wptr = 0; in tee_submit_cmd()
310 iowrite32(tee->rb_mgr.wptr, tee->io_regs + tee->vdata->ring_wptr_reg); in tee_submit_cmd()
/linux/drivers/gpu/drm/radeon/
H A Dradeon_ring.c89 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
130 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
178 while (ring->wptr & ring->align_mask) { in radeon_ring_commit()
216 ring->wptr = ring->wptr_old; in radeon_ring_undo()
316 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
472 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info_show() local
478 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info_show()
480 wptr, wptr); in radeon_debugfs_ring_info_show()
494 ring->wptr, ring->wptr); in radeon_debugfs_ring_info_show()
H A Dvce_v1_0.c98 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
100 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
299 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
305 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
306 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Drpc.c153 u32 wptr = *gsp->msgq.wptr; in r535_gsp_msgq_wait() local
155 used = wptr + gsp->msgq.cnt - rptr; in r535_gsp_msgq_wait()
361 u32 wptr, size, step, len; in r535_gsp_cmdq_push() local
377 wptr = *gsp->cmdq.wptr; in r535_gsp_cmdq_push()
380 free = *gsp->cmdq.rptr + gsp->cmdq.cnt - wptr - 1; in r535_gsp_cmdq_push()
394 cqe = (void *)((u8 *)gsp->shm.cmdq.ptr + 0x1000 + wptr * 0x1000); in r535_gsp_cmdq_push()
395 step = min_t(u32, free, (gsp->cmdq.cnt - wptr)); in r535_gsp_cmdq_push()
400 wptr += DIV_ROUND_UP(size, 0x1000); in r535_gsp_cmdq_push()
401 if (wptr == gsp->cmdq.cnt) in r535_gsp_cmdq_push()
402 wptr = 0; in r535_gsp_cmdq_push()
[all …]
/linux/Documentation/admin-guide/blockdev/
H A Dzoned_loop.rst162 …start: 0x000000000, len 0x020000, cap 0x020000, wptr 0x000000 reset:0 non-seq:0, zcond: 0(nw) [typ…
163 …start: 0x000020000, len 0x020000, cap 0x020000, wptr 0x000000 reset:0 non-seq:0, zcond: 0(nw) [typ…
164 …start: 0x000040000, len 0x020000, cap 0x020000, wptr 0x000000 reset:0 non-seq:0, zcond: 0(nw) [typ…
165 …start: 0x000060000, len 0x020000, cap 0x020000, wptr 0x000000 reset:0 non-seq:0, zcond: 0(nw) [typ…
166 …start: 0x000080000, len 0x020000, cap 0x020000, wptr 0x000000 reset:0 non-seq:0, zcond: 0(nw) [typ…
167 …start: 0x0000a0000, len 0x020000, cap 0x020000, wptr 0x000000 reset:0 non-seq:0, zcond: 0(nw) [typ…
168 …start: 0x0000c0000, len 0x020000, cap 0x020000, wptr 0x000000 reset:0 non-seq:0, zcond: 0(nw) [typ…
169 …start: 0x0000e0000, len 0x020000, cap 0x020000, wptr 0x000000 reset:0 non-seq:0, zcond: 0(nw) [typ…
170 …start: 0x000100000, len 0x020000, cap 0x01f800, wptr 0x000000 reset:0 non-seq:0, zcond: 1(em) [typ…
171 …start: 0x000120000, len 0x020000, cap 0x01f800, wptr 0x000000 reset:0 non-seq:0, zcond: 1(em) [typ…
/linux/drivers/video/fbdev/
H A Dmaxinefb.c67 unsigned char *wptr; in maxinefb_ims332_write_register() local
69 wptr = regs + 0xa0000 + (regno << 4); in maxinefb_ims332_write_register()
71 *((volatile unsigned short *) (wptr)) = val; in maxinefb_ims332_write_register()
/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_preempt.c43 uint32_t wptr; in update_wptr() local
49 wptr = get_wptr(ring); in update_wptr()
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
149 a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring); in a5xx_preempt_trigger()
233 a5xx_gpu->preempt[i]->wptr = 0; in a5xx_preempt_hw_init()

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