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Searched refs:wp (Results 1 – 25 of 534) sorted by relevance

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/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_wp.c20 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
44 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
46 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
49 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
51 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
53 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
56 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
58 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
61 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
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H A Dhdmi.h239 struct hdmi_wp_data *wp; member
261 struct hdmi_wp_data *wp; member
296 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
297 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
298 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
299 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
300 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
301 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
302 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
303 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
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H A Dhdmi5.c68 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler() local
71 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
72 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
84 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
96 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
99 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
104 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
106 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
172 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff); in hdmi_power_on_full()
173 hdmi_wp_set_irqstatus(&hdmi->wp, in hdmi_power_on_full()
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H A Dhdmi4.c67 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler() local
70 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
71 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
83 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
86 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
88 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
90 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
150 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_power_on_full() local
159 hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE); in hdmi_power_on_full()
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H A Dhdmi_pll.c42 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
50 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
60 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
63 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
147 if (hpll->wp->version == 4) in hdmi_init_pll_data()
162 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) in hdmi_pll_init() argument
167 pll->wp = wp; in hdmi_pll_init()
H A Dhdmi4_cec.c164 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
165 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
166 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
178 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); in hdmi_cec_adap_enable()
201 hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
238 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
326 struct hdmi_wp_data *wp) in hdmi4_cec_init() argument
337 core->wp = wp; in hdmi4_cec_init()
340 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi4_cec_init()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_wp.c21 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
45 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
47 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
50 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
52 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
54 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
57 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
59 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
62 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
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H A Dhdmi.h233 struct hdmi_wp_data *wp; member
277 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
278 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
279 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
280 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
281 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
282 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
283 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
284 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
285 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
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H A Dhdmi5.c65 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
68 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
69 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
93 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
96 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
101 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
103 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
178 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); in hdmi_power_on_full()
179 hdmi_wp_set_irqstatus(&hdmi.wp, in hdmi_power_on_full()
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H A Dhdmi4.c61 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
64 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
65 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
75 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
77 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
80 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
82 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
84 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
148 struct hdmi_wp_data *wp = &hdmi.wp; in hdmi_power_on_full() local
156 hdmi_wp_clear_irqenable(wp, 0xffffffff); in hdmi_power_on_full()
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H A Dhdmi_pll.c102 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
106 return hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
112 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
114 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
209 struct hdmi_wp_data *wp) in hdmi_pll_init() argument
213 pll->wp = wp; in hdmi_pll_init()
/linux/arch/powerpc/math-emu/
H A Dmath_efp.c109 u32 wp[2]; member
200 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
201 vc.wp[1] = regs->gpr[fc]; in do_spe_mathemu()
202 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
203 va.wp[1] = regs->gpr[fa]; in do_spe_mathemu()
204 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
205 vb.wp[1] = regs->gpr[fb]; in do_spe_mathemu()
210 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
211 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
212 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
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/linux/lib/crypto/mpi/
H A Dmpi-mul.c19 mpi_ptr_t up, vp, wp; in mpi_mul() local
43 wp = w->d; in mpi_mul()
48 if (wp == up || wp == vp) { in mpi_mul()
49 wp = mpi_alloc_limb_space(wsize); in mpi_mul()
50 if (!wp) in mpi_mul()
57 wp = w->d; in mpi_mul()
60 if (wp == up) { in mpi_mul()
66 if (wp == vp) in mpi_mul()
69 MPN_COPY(up, wp, usize); in mpi_mul()
70 } else if (wp == vp) { in mpi_mul()
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H A Dmpi-add.c18 mpi_ptr_t wp, up, vp; in mpi_add() local
48 wp = w->d; in mpi_add()
52 MPN_COPY(wp, up, usize); in mpi_add()
58 mpihelp_sub(wp, up, usize, vp, vsize); in mpi_add()
60 MPN_NORMALIZE(wp, wsize); in mpi_add()
63 mpihelp_sub_n(wp, vp, up, usize); in mpi_add()
65 MPN_NORMALIZE(wp, wsize); in mpi_add()
69 mpihelp_sub_n(wp, up, vp, usize); in mpi_add()
71 MPN_NORMALIZE(wp, wsize); in mpi_add()
76 mpi_limb_t cy = mpihelp_add(wp, up, usize, vp, vsize); in mpi_add()
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H A Dgeneric_mpih-lshift.c28 mpihelp_lshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned int cnt) in mpihelp_lshift() argument
36 wp += 1; in mpihelp_lshift()
44 wp[i] = (high_limb << sh_1) | (low_limb >> sh_2); in mpihelp_lshift()
47 wp[i] = high_limb << sh_1; in mpihelp_lshift()
H A Dgeneric_mpih-rshift.c29 mpihelp_rshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned cnt) in mpihelp_rshift() argument
37 wp -= 1; in mpihelp_rshift()
44 wp[i] = (low_limb >> sh_1) | (high_limb << sh_2); in mpihelp_rshift()
47 wp[i] = low_limb >> sh_1; in mpihelp_rshift()
/linux/fs/bcachefs/
H A Dalloc_foreground.c842 struct write_point *wp, in bucket_alloc_from_stripe() argument
871 devs_sorted = bch2_dev_alloc_list(c, &wp->stripe, devs_may_alloc); in bucket_alloc_from_stripe()
900 struct write_point *wp, in want_bucket() argument
910 if (ob->data_type != wp->data_type) in want_bucket()
914 (wp->data_type == BCH_DATA_btree || ec || *have_cache)) in want_bucket()
925 struct write_point *wp, in bucket_alloc_set_writepoint() argument
937 open_bucket_for_each(c, &wp->ptrs, ob, i) { in bucket_alloc_set_writepoint()
938 if (!ret && want_bucket(c, wp, devs_may_alloc, in bucket_alloc_set_writepoint()
946 wp->ptrs = ptrs_skip; in bucket_alloc_set_writepoint()
953 struct write_point *wp, in bucket_alloc_set_partial() argument
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H A Dalloc_foreground.h91 static inline void bch2_alloc_sectors_done_inlined(struct bch_fs *c, struct write_point *wp) in bch2_alloc_sectors_done_inlined() argument
97 open_bucket_for_each(c, &wp->ptrs, ob, i) in bch2_alloc_sectors_done_inlined()
99 wp->ptrs = keep; in bch2_alloc_sectors_done_inlined()
101 mutex_unlock(&wp->lock); in bch2_alloc_sectors_done_inlined()
107 struct write_point *wp, in bch2_open_bucket_get() argument
113 open_bucket_for_each(c, &wp->ptrs, ob, i) { in bch2_open_bucket_get()
114 ob->data_type = wp->data_type; in bch2_open_bucket_get()
182 bch2_alloc_sectors_append_ptrs_inlined(struct bch_fs *c, struct write_point *wp, in bch2_alloc_sectors_append_ptrs_inlined() argument
189 BUG_ON(sectors > wp->sectors_free); in bch2_alloc_sectors_append_ptrs_inlined()
190 wp->sectors_free -= sectors; in bch2_alloc_sectors_append_ptrs_inlined()
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H A Dio_write.c561 static inline void __wp_update_state(struct write_point *wp, enum write_point_state state) in __wp_update_state() argument
563 if (state != wp->state) { in __wp_update_state()
566 if (wp->last_state_change && in __wp_update_state()
567 time_after64(now, wp->last_state_change)) in __wp_update_state()
568 wp->time[wp->state] += now - wp->last_state_change; in __wp_update_state()
569 wp->state = state; in __wp_update_state()
570 wp->last_state_change = now; in __wp_update_state()
574 static inline void wp_update_state(struct write_point *wp, bool running) in wp_update_state() argument
579 !list_empty(&wp->writes) ? WRITE_POINT_waiting_io in wp_update_state()
582 __wp_update_state(wp, state); in wp_update_state()
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/linux/tools/testing/selftests/breakpoints/
H A Dbreakpoint_test_arm64.c81 static bool set_watchpoint(pid_t pid, int size, int wp) in set_watchpoint() argument
83 const volatile uint8_t *addr = &var[32 + wp]; in set_watchpoint()
112 static bool run_test(int wr_size, int wp_size, int wr, int wp) in run_test() argument
143 if (!set_watchpoint(pid, wp_size, wp)) in run_test()
204 int wr, wp, size; in main() local
216 for (wp = wr - size; wp <= wr + size; wp = wp + size) { in main()
217 result = run_test(size, MIN(size, 8), wr, wp); in main()
218 if ((result && wr == wp) || in main()
219 (!result && wr != wp)) in main()
222 size, wr, wp); in main()
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/linux/sound/hda/
H A Dhdac_controller.c71 bus->rirb.wp = bus->rirb.rp = 0; in snd_hdac_bus_init_cmd_io()
229 unsigned int wp, rp; in snd_hdac_bus_send_cmd_corb() local
236 wp = snd_hdac_chip_readw(bus, CORBWP); in snd_hdac_bus_send_cmd_corb()
237 if (wp == 0xffff) { in snd_hdac_bus_send_cmd_corb()
242 wp++; in snd_hdac_bus_send_cmd_corb()
243 wp %= AZX_MAX_CORB_ENTRIES; in snd_hdac_bus_send_cmd_corb()
246 if (wp == rp) { in snd_hdac_bus_send_cmd_corb()
253 bus->corb.buf[wp] = cpu_to_le32(val); in snd_hdac_bus_send_cmd_corb()
254 snd_hdac_chip_writew(bus, CORBWP, wp); in snd_hdac_bus_send_cmd_corb()
272 unsigned int rp, wp; in snd_hdac_bus_update_rirb() local
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/linux/lib/raid6/
H A Dneon.uc63 register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
71 wq$$ = wp$$ = vld1q_u8(&dptr[z0][d+$$*NSIZE]);
74 wp$$ = veorq_u8(wp$$, wd$$);
82 vst1q_u8(&p[d+NSIZE*$$], wp$$);
94 register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
103 wp$$ = veorq_u8(vld1q_u8(&p[d+$$*NSIZE]), wq$$);
108 wp$$ = veorq_u8(wp$$, wd$$);
150 vst1q_u8(&p[d+NSIZE*$$], wp$$);
H A Dint.uc81 unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
88 wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
91 wp$$ ^= wd$$;
98 *(unative_t *)&p[d+NSIZE*$$] = wp$$;
110 unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
118 wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
121 wp$$ ^= wd$$;
135 *(unative_t *)&p[d+NSIZE*$$] ^= wp$$;
/linux/arch/arm/kernel/
H A Dhw_breakpoint.c733 struct perf_event *wp, **slots; in watchpoint_handler() local
745 wp = slots[i]; in watchpoint_handler()
746 if (wp == NULL) in watchpoint_handler()
757 info = counter_arch_bp(wp); in watchpoint_handler()
758 info->trigger = wp->attr.bp_addr; in watchpoint_handler()
764 if (!(access & hw_breakpoint_type(wp))) in watchpoint_handler()
781 info = counter_arch_bp(wp); in watchpoint_handler()
795 perf_bp_event(wp, regs); in watchpoint_handler()
802 if (!is_default_overflow_handler(wp)) in watchpoint_handler()
805 enable_single_step(wp, instruction_pointer(regs)); in watchpoint_handler()
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/linux/sound/pci/lola/
H A Dlola.c88 unsigned int wp = chip->corb.wp + 1; in corb_send_verb() local
89 wp %= LOLA_CORB_ENTRIES; in corb_send_verb()
90 chip->corb.wp = wp; in corb_send_verb()
91 chip->corb.buf[wp * 2] = cpu_to_le32(data); in corb_send_verb()
92 chip->corb.buf[wp * 2 + 1] = cpu_to_le32(extdata); in corb_send_verb()
93 lola_writew(chip, BAR0, CORBWP, wp); in corb_send_verb()
111 unsigned int rp, wp; in lola_update_rirb() local
114 wp = lola_readw(chip, BAR0, RIRBWP); in lola_update_rirb()
115 if (wp == chip->rirb.wp) in lola_update_rirb()
117 chip->rirb.wp = wp; in lola_update_rirb()
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