Home
last modified time | relevance | path

Searched refs:wp (Results 1 – 25 of 586) sorted by relevance

12345678910>>...24

/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_wp.c20 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
44 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
46 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
49 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
51 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
53 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
56 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
58 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
61 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
[all …]
H A Dhdmi.h239 struct hdmi_wp_data *wp; member
261 struct hdmi_wp_data *wp; member
296 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
297 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
298 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
299 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
300 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
301 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
302 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
303 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
[all …]
H A Dhdmi_pll.c42 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
50 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
60 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
63 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
147 if (hpll->wp->version == 4) in hdmi_init_pll_data()
162 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) in hdmi_pll_init() argument
167 pll->wp = wp; in hdmi_pll_init()
H A Dhdmi4_cec.c164 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
165 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
166 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
178 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); in hdmi_cec_adap_enable()
201 hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
238 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
326 struct hdmi_wp_data *wp) in hdmi4_cec_init() argument
337 core->wp = wp; in hdmi4_cec_init()
340 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi4_cec_init()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_wp.c21 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
45 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
47 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
50 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
52 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
54 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
57 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
59 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
62 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
[all …]
H A Dhdmi.h233 struct hdmi_wp_data *wp; member
277 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
278 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
279 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
280 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
281 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
282 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
283 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
284 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
285 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
[all …]
H A Dhdmi5.c65 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
68 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
69 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
93 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
96 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
101 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
103 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
178 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); in hdmi_power_on_full()
179 hdmi_wp_set_irqstatus(&hdmi.wp, in hdmi_power_on_full()
[all …]
H A Dhdmi4.c61 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
64 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
65 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
75 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
77 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
80 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
82 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
84 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
148 struct hdmi_wp_data *wp = &hdmi.wp; in hdmi_power_on_full() local
156 hdmi_wp_clear_irqenable(wp, 0xffffffff); in hdmi_power_on_full()
[all …]
H A Dhdmi_pll.c102 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
106 return hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
112 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
114 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
209 struct hdmi_wp_data *wp) in hdmi_pll_init() argument
213 pll->wp = wp; in hdmi_pll_init()
H A Dhdmi4_core.h253 void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
258 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
259 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
260 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
/linux/arch/powerpc/math-emu/
H A Dmath_efp.c109 u32 wp[2]; member
200 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
201 vc.wp[1] = regs->gpr[fc]; in do_spe_mathemu()
202 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
203 va.wp[1] = regs->gpr[fa]; in do_spe_mathemu()
204 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
205 vb.wp[1] = regs->gpr[fb]; in do_spe_mathemu()
210 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
211 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
212 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
[all …]
/linux/lib/crypto/mpi/
H A Dmpi-mul.c21 mpi_ptr_t up, vp, wp; in mpi_mul() local
45 wp = w->d; in mpi_mul()
50 if (wp == up || wp == vp) { in mpi_mul()
51 wp = mpi_alloc_limb_space(wsize); in mpi_mul()
52 if (!wp) in mpi_mul()
59 wp = w->d; in mpi_mul()
62 if (wp == up) { in mpi_mul()
68 if (wp == vp) in mpi_mul()
71 MPN_COPY(up, wp, usize); in mpi_mul()
72 } else if (wp == vp) { in mpi_mul()
[all …]
H A Dmpi-add.c20 mpi_ptr_t wp, up, vp; in mpi_add() local
50 wp = w->d; in mpi_add()
54 MPN_COPY(wp, up, usize); in mpi_add()
60 mpihelp_sub(wp, up, usize, vp, vsize); in mpi_add()
62 MPN_NORMALIZE(wp, wsize); in mpi_add()
65 mpihelp_sub_n(wp, vp, up, usize); in mpi_add()
67 MPN_NORMALIZE(wp, wsize); in mpi_add()
71 mpihelp_sub_n(wp, up, vp, usize); in mpi_add()
73 MPN_NORMALIZE(wp, wsize); in mpi_add()
78 mpi_limb_t cy = mpihelp_add(wp, up, usize, vp, vsize); in mpi_add()
[all …]
H A Dgeneric_mpih-lshift.c28 mpihelp_lshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned int cnt) in mpihelp_lshift() argument
36 wp += 1; in mpihelp_lshift()
44 wp[i] = (high_limb << sh_1) | (low_limb >> sh_2); in mpihelp_lshift()
47 wp[i] = high_limb << sh_1; in mpihelp_lshift()
H A Dgeneric_mpih-rshift.c29 mpihelp_rshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned cnt) in mpihelp_rshift() argument
37 wp -= 1; in mpihelp_rshift()
44 wp[i] = (low_limb >> sh_1) | (high_limb << sh_2); in mpihelp_rshift()
47 wp[i] = low_limb >> sh_1; in mpihelp_rshift()
/linux/tools/testing/selftests/breakpoints/
H A Dbreakpoint_test_arm64.c81 static bool set_watchpoint(pid_t pid, int size, int wp) in set_watchpoint() argument
83 const volatile uint8_t *addr = &var[32 + wp]; in set_watchpoint()
112 static bool run_test(int wr_size, int wp_size, int wr, int wp) in run_test() argument
143 if (!set_watchpoint(pid, wp_size, wp)) in run_test()
204 int wr, wp, size; in main() local
216 for (wp = wr - size; wp <= wr + size; wp = wp + size) { in main()
217 result = run_test(size, MIN(size, 8), wr, wp); in main()
218 if ((result && wr == wp) || in main()
219 (!result && wr != wp)) in main()
222 size, wr, wp); in main()
[all …]
/linux/sound/hda/core/
H A Dcontroller.c71 bus->rirb.wp = bus->rirb.rp = 0; in snd_hdac_bus_init_cmd_io()
222 unsigned int wp, rp; in snd_hdac_bus_send_cmd_corb() local
229 wp = snd_hdac_chip_readw(bus, CORBWP); in snd_hdac_bus_send_cmd_corb()
230 if (wp == 0xffff) { in snd_hdac_bus_send_cmd_corb()
234 wp++; in snd_hdac_bus_send_cmd_corb()
235 wp %= AZX_MAX_CORB_ENTRIES; in snd_hdac_bus_send_cmd_corb()
238 if (wp == rp) { in snd_hdac_bus_send_cmd_corb()
244 bus->corb.buf[wp] = cpu_to_le32(val); in snd_hdac_bus_send_cmd_corb()
245 snd_hdac_chip_writew(bus, CORBWP, wp); in snd_hdac_bus_send_cmd_corb()
261 unsigned int rp, wp; in snd_hdac_bus_update_rirb() local
[all …]
H A Dbus.c147 unsigned int wp; in snd_hdac_bus_queue_event() local
153 wp = (bus->unsol_wp + 1) % HDA_UNSOL_QUEUE_SIZE; in snd_hdac_bus_queue_event()
154 bus->unsol_wp = wp; in snd_hdac_bus_queue_event()
156 wp <<= 1; in snd_hdac_bus_queue_event()
157 bus->unsol_queue[wp] = res; in snd_hdac_bus_queue_event()
158 bus->unsol_queue[wp + 1] = res_ex; in snd_hdac_bus_queue_event()
/linux/lib/raid6/
H A Dneon.uc63 register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
71 wq$$ = wp$$ = vld1q_u8(&dptr[z0][d+$$*NSIZE]);
74 wp$$ = veorq_u8(wp$$, wd$$);
82 vst1q_u8(&p[d+NSIZE*$$], wp$$);
94 register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
103 wp$$ = veorq_u8(vld1q_u8(&p[d+$$*NSIZE]), wq$$);
108 wp$$ = veorq_u8(wp$$, wd$$);
150 vst1q_u8(&p[d+NSIZE*$$], wp$$);
H A Dint.uc81 unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
88 wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
91 wp$$ ^= wd$$;
98 *(unative_t *)&p[d+NSIZE*$$] = wp$$;
110 unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
118 wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
121 wp$$ ^= wd$$;
135 *(unative_t *)&p[d+NSIZE*$$] ^= wp$$;
H A Dvpermxor.uc49 unative_t wp$$, wq$$, wd$$;
56 wp$$ = wq$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
61 wp$$ = vec_xor(wp$$, wd$$);
67 *(unative_t *)&p[d+NSIZE*$$] = wp$$;
/linux/arch/arm/kernel/
H A Dhw_breakpoint.c733 struct perf_event *wp, **slots; in watchpoint_handler() local
745 wp = slots[i]; in watchpoint_handler()
746 if (wp == NULL) in watchpoint_handler()
757 info = counter_arch_bp(wp); in watchpoint_handler()
758 info->trigger = wp->attr.bp_addr; in watchpoint_handler()
764 if (!(access & hw_breakpoint_type(wp))) in watchpoint_handler()
781 info = counter_arch_bp(wp); in watchpoint_handler()
795 perf_bp_event(wp, regs); in watchpoint_handler()
802 if (!is_default_overflow_handler(wp)) in watchpoint_handler()
805 enable_single_step(wp, instruction_pointer(regs)); in watchpoint_handler()
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Dpci.h154 static inline int avail_desc(u32 wp, u32 rp, u32 len) in avail_desc() argument
156 if (rp > wp) in avail_desc()
157 return rp - wp - 1; in avail_desc()
159 return len - wp + rp - 1; in avail_desc()
183 u32 wp; member
276 buf_desc = ring->r.head + ring->r.wp * size; in get_tx_buffer_desc()
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-mighty.dts23 wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
25 /delete-property/ disable-wp;
30 sdmmc_wp_pin: sdmmc-wp-pin {
/linux/tools/testing/selftests/mm/
H A Duffd-unit-tests.c207 #define pagemap_check_wp(value, wp) do { \ argument
208 if (!!(value & PM_UFFD_WP) != wp) \
658 static int faulting_process(uffd_global_test_opts_t *gopts, int signal_test, bool wp) in faulting_process() argument
693 if (copy_page(gopts, offset, wp)) in faulting_process()
756 static void uffd_sigbus_test_common(uffd_global_test_opts_t *gopts, bool wp) in uffd_sigbus_test_common() argument
771 true, wp, false)) in uffd_sigbus_test_common()
774 if (faulting_process(gopts, 1, wp)) in uffd_sigbus_test_common()
779 args.apply_wp = wp; in uffd_sigbus_test_common()
791 exit(faulting_process(gopts, 2, wp)); in uffd_sigbus_test_common()
817 static void uffd_events_test_common(uffd_global_test_opts_t *gopts, bool wp) in uffd_events_test_common() argument
[all …]

12345678910>>...24