Searched refs:wcreg (Results 1 – 4 of 4) sorted by relevance
184 u32 wcreg; /* cached write control register value */ member 222 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)386 writel(rme32->wcreg | RME32_WCR_PD, in snd_rme32_reset_dac() 388 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); in snd_rme32_playback_getrate() 395 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + in snd_rme32_playback_getrate() 396 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); in snd_rme32_playback_getrate() 410 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; in snd_rme32_capture_getrate() 478 ds = rme32->wcreg & RME32_WCR_DS_BM; in snd_rme32_playback_setrate() 481 rme32->wcreg &= ~RME32_WCR_DS_BM; in snd_rme32_playback_setrate() 482 rme32->wcreg in snd_rme32_playback_setrate() [all...]
214 u32 wcreg; /* cached write control register value */ member 254 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)255 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)514 writel(rme96->wcreg | RME96_WCR_PD, in snd_rme96_reset_dac() 516 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);522 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +523 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);531 rme96->wcreg |= RME96_WCR_MONITOR_0; in snd_rme96_setmontracks() 533 rme96->wcreg &= ~RME96_WCR_MONITOR_0; in snd_rme96_setmontracks() 536 rme96->wcreg | in snd_rme96_setmontracks() [all...]
254 struct bnxt_qplib_reg_desc wcreg; member
110 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; in bnxt_re_set_db_offset()114 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset; in bnxt_re_set_db_offset()124 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; in bnxt_re_set_db_offset()