Home
last modified time | relevance | path

Searched refs:wcl_cs_reg (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3441 uint32_t wcl_cs_reg; in gfx_v9_4_3_emit_wave_limit_cs() local
3448 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); in gfx_v9_4_3_emit_wave_limit_cs()
3451 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); in gfx_v9_4_3_emit_wave_limit_cs()
3454 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); in gfx_v9_4_3_emit_wave_limit_cs()
3457 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); in gfx_v9_4_3_emit_wave_limit_cs()
3464 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_4_3_emit_wave_limit_cs()
H A Dgfx_v8_0.c6854 uint32_t wcl_cs_reg; in gfx_v8_0_emit_wave_limit_cs() local
6860 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0; in gfx_v8_0_emit_wave_limit_cs()
6863 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1; in gfx_v8_0_emit_wave_limit_cs()
6866 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2; in gfx_v8_0_emit_wave_limit_cs()
6869 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3; in gfx_v8_0_emit_wave_limit_cs()
6876 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v8_0_emit_wave_limit_cs()
H A Dgfx_v9_0.c7153 uint32_t wcl_cs_reg; in gfx_v9_0_emit_wave_limit_cs() local
7160 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); in gfx_v9_0_emit_wave_limit_cs()
7163 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); in gfx_v9_0_emit_wave_limit_cs()
7166 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); in gfx_v9_0_emit_wave_limit_cs()
7169 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); in gfx_v9_0_emit_wave_limit_cs()
7176 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_0_emit_wave_limit_cs()