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Searched refs:wb_gpu_addr (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v7_1.c855 uint64_t wb_gpu_addr; in sdma_v7_1_mqd_init() local
866 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v7_1_mqd_init()
867 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v7_1_mqd_init()
868 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v7_1_mqd_init()
870 wb_gpu_addr = prop->rptr_gpu_addr; in sdma_v7_1_mqd_init()
871 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v7_1_mqd_init()
872 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v7_1_mqd_init()
H A Dsdma_v7_0.c862 uint64_t wb_gpu_addr; in sdma_v7_0_mqd_init() local
873 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v7_0_mqd_init()
874 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v7_0_mqd_init()
875 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v7_0_mqd_init()
877 wb_gpu_addr = prop->rptr_gpu_addr; in sdma_v7_0_mqd_init()
878 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v7_0_mqd_init()
879 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v7_0_mqd_init()
H A Dsdma_v6_0.c844 uint64_t wb_gpu_addr; in sdma_v6_0_mqd_init() local
855 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v6_0_mqd_init()
856 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v6_0_mqd_init()
857 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v6_0_mqd_init()
859 wb_gpu_addr = prop->rptr_gpu_addr; in sdma_v6_0_mqd_init()
860 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v6_0_mqd_init()
861 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v6_0_mqd_init()
H A Dsdma_v5_0.c963 uint64_t wb_gpu_addr; in sdma_v5_0_mqd_init() local
977 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v5_0_mqd_init()
978 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v5_0_mqd_init()
979 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v5_0_mqd_init()
981 wb_gpu_addr = prop->rptr_gpu_addr; in sdma_v5_0_mqd_init()
982 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v5_0_mqd_init()
983 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v5_0_mqd_init()
H A Dsdma_v5_2.c863 uint64_t wb_gpu_addr; in sdma_v5_2_mqd_init() local
877 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v5_2_mqd_init()
878 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v5_2_mqd_init()
879 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v5_2_mqd_init()
881 wb_gpu_addr = prop->rptr_gpu_addr; in sdma_v5_2_mqd_init()
882 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); in sdma_v5_2_mqd_init()
883 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); in sdma_v5_2_mqd_init()
H A Dmes_v11_0.c1418 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in mes_v11_0_mqd_init() local
1463 wb_gpu_addr = ring->rptr_gpu_addr; in mes_v11_0_mqd_init()
1464 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in mes_v11_0_mqd_init()
1466 upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v11_0_mqd_init()
1469 wb_gpu_addr = ring->wptr_gpu_addr; in mes_v11_0_mqd_init()
1470 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; in mes_v11_0_mqd_init()
1471 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v11_0_mqd_init()
H A Dmes_v12_1.c1265 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in mes_v12_1_mqd_init() local
1308 wb_gpu_addr = ring->rptr_gpu_addr; in mes_v12_1_mqd_init()
1309 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in mes_v12_1_mqd_init()
1311 upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v12_1_mqd_init()
1314 wb_gpu_addr = ring->wptr_gpu_addr; in mes_v12_1_mqd_init()
1315 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; in mes_v12_1_mqd_init()
1316 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v12_1_mqd_init()
H A Dmes_v12_0.c1489 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in mes_v12_0_mqd_init() local
1532 wb_gpu_addr = ring->rptr_gpu_addr; in mes_v12_0_mqd_init()
1533 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in mes_v12_0_mqd_init()
1535 upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v12_0_mqd_init()
1538 wb_gpu_addr = ring->wptr_gpu_addr; in mes_v12_0_mqd_init()
1539 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; in mes_v12_0_mqd_init()
1540 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v12_0_mqd_init()
H A Dgfx_v12_0.c3007 uint64_t hqd_gpu_addr, wb_gpu_addr; in gfx_v12_0_gfx_mqd_init()
3048 wb_gpu_addr = prop->rptr_gpu_addr; in gfx_v12_0_gfx_mqd_init()
3049 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v12_0_gfx_mqd_init()
3051 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v12_0_gfx_mqd_init()
3054 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v12_0_gfx_mqd_init()
3055 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v12_0_gfx_mqd_init()
3056 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v12_0_gfx_mqd_init()
3182 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v12_0_compute_mqd_init()
3260 wb_gpu_addr = prop->rptr_gpu_addr; in gfx_v12_0_compute_mqd_init()
3261 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr in gfx_v12_0_compute_mqd_init()
3006 uint64_t hqd_gpu_addr, wb_gpu_addr; gfx_v12_0_gfx_mqd_init() local
3180 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; gfx_v12_0_compute_mqd_init() local
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H A Dgfx_v11_0.c4167 uint64_t hqd_gpu_addr, wb_gpu_addr; in gfx_v11_0_gfx_mqd_init()
4205 wb_gpu_addr = prop->rptr_gpu_addr; in gfx_v11_0_gfx_mqd_init()
4206 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
4208 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
4211 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v11_0_gfx_mqd_init()
4212 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
4213 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
4341 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v11_0_compute_mqd_init()
4420 wb_gpu_addr = prop->rptr_gpu_addr; in gfx_v11_0_compute_mqd_init()
4421 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr in gfx_v11_0_compute_mqd_init()
4166 uint64_t hqd_gpu_addr, wb_gpu_addr; gfx_v11_0_gfx_mqd_init() local
4339 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; gfx_v11_0_compute_mqd_init() local
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H A Dgfx_v9_4_3.c1764 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v9_4_3_xcc_mqd_init() local
1852 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v9_4_3_xcc_mqd_init()
1853 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v9_4_3_xcc_mqd_init()
1855 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v9_4_3_xcc_mqd_init()
1858 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_4_3_xcc_mqd_init()
1859 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v9_4_3_xcc_mqd_init()
1860 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v9_4_3_xcc_mqd_init()
H A Dgfx_v12_1.c2444 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v12_1_compute_mqd_init() local
2518 wb_gpu_addr = prop->rptr_gpu_addr; in gfx_v12_1_compute_mqd_init()
2519 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v12_1_compute_mqd_init()
2521 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v12_1_compute_mqd_init()
2524 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v12_1_compute_mqd_init()
2525 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v12_1_compute_mqd_init()
2526 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v12_1_compute_mqd_init()
H A Dgfx_v10_0.c6777 uint64_t hqd_gpu_addr, wb_gpu_addr; in gfx_v10_0_gfx_mqd_init() local
6815 wb_gpu_addr = prop->rptr_gpu_addr; in gfx_v10_0_gfx_mqd_init()
6816 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_gfx_mqd_init()
6818 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v10_0_gfx_mqd_init()
6821 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v10_0_gfx_mqd_init()
6822 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_gfx_mqd_init()
6823 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v10_0_gfx_mqd_init()
6921 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v10_0_compute_mqd_init() local
6999 wb_gpu_addr = prop->rptr_gpu_addr; in gfx_v10_0_compute_mqd_init()
7000 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_compute_mqd_init()
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H A Dgfx_v8_0.c4416 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v8_0_mqd_init() local
4479 wb_gpu_addr = ring->rptr_gpu_addr; in gfx_v8_0_mqd_init()
4480 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()
4482 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v8_0_mqd_init()
4485 wb_gpu_addr = ring->wptr_gpu_addr; in gfx_v8_0_mqd_init()
4486 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()
4487 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v8_0_mqd_init()
H A Dgfx_v9_0.c3554 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v9_0_mqd_init() local
3643 wb_gpu_addr = ring->rptr_gpu_addr; in gfx_v9_0_mqd_init()
3644 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v9_0_mqd_init()
3646 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v9_0_mqd_init()
3649 wb_gpu_addr = ring->wptr_gpu_addr; in gfx_v9_0_mqd_init()
3650 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v9_0_mqd_init()
3651 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v9_0_mqd_init()