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Searched refs:wave (Results 1 – 15 of 15) sorted by relevance

/linux/sound/pci/emu10k1/
H A Demu10k1.c76 struct snd_seq_device *wave = NULL; in snd_card_emu10k1_probe() local
151 sizeof(struct snd_emu10k1_synth_arg), &wave) < 0 || in snd_card_emu10k1_probe()
152 wave == NULL) { in snd_card_emu10k1_probe()
157 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in snd_card_emu10k1_probe()
158 strscpy(wave->name, "Emu-10k1 Synth"); in snd_card_emu10k1_probe()
/linux/sound/pci/au88x0/
H A Dau88x0.c266 sizeof(snd_vortex_synth_arg_t), &wave) < 0 in __snd_vortex_probe()
267 || wave == NULL) { in __snd_vortex_probe()
272 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in __snd_vortex_probe()
273 strscpy(wave->name, "Aureal Synth"); in __snd_vortex_probe()
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
19 wave input on the OSCIN pin instead of using a crystal oscillator.
61 ti,clkmode-square-wave;
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_1.c753 uint32_t xcc_id, uint32_t wave, in wave_read_ind()
757 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
763 uint32_t xcc_id, uint32_t wave, in wave_read_regs() argument
768 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
778 uint32_t simd, uint32_t wave, in gfx_v12_1_read_wave_data() argument
788 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATUS); in gfx_v12_1_read_wave_data()
789 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_LO); in gfx_v12_1_read_wave_data()
790 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_HI); in gfx_v12_1_read_wave_data()
791 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_LO); in gfx_v12_1_read_wave_data()
792 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_HI); in gfx_v12_1_read_wave_data()
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H A Damdgpu_umr.h50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Dgfx_v12_0.c824 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
827 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
832 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
837 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
847 uint32_t simd, uint32_t wave, in gfx_v12_0_read_wave_data() argument
855 /* type 4 wave data */ in gfx_v12_0_read_wave_data()
857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v12_0_read_wave_data()
858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v12_0_read_wave_data()
859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v12_0_read_wave_data()
860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_L in gfx_v12_0_read_wave_data()
884 gfx_v12_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst) gfx_v12_0_read_wave_sgprs() argument
896 gfx_v12_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst) gfx_v12_0_read_wave_vgprs() argument
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H A Dgfx_v9_4_3.c715 …ad_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) in wave_read_ind() argument
718 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
726 uint32_t wave, uint32_t thread, in wave_read_regs() argument
730 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
741 uint32_t xcc_id, uint32_t simd, uint32_t wave, in gfx_v9_4_3_read_wave_data() argument
746 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_read_wave_data()
747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_3_read_wave_data()
748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_4_3_read_wave_data()
749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_3_read_wave_data()
750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_3_read_wave_data()
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H A Damdgpu_debugfs.c452 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
457 adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread, *pos, size>>2, data); in amdgpu_debugfs_gprwave_read()
460 adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, data); in amdgpu_debugfs_gprwave_read()
1159 * The offset being sought changes which wave that the status data in amdgpu_debugfs_wave_read()
1179 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read()
1189 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read()
1210 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
1242 /** amdgpu_debugfs_gpr_read - Read wave gprs
1249 * The offset being sought changes which wave that the status data in amdgpu_debugfs_gpr_read()
1270 uint32_t offset, se, sh, cu, wave, sim in amdgpu_debugfs_gpr_read()
1164 uint32_t offset, se, sh, cu, wave, simd, data[32]; amdgpu_debugfs_wave_read() local
1255 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; amdgpu_debugfs_gpr_read() local
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H A Dgfx_v8_0.c5066 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5069 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
5077 uint32_t wave, uint32_t thread, in wave_read_regs() argument
5081 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
5091 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v8_0_read_wave_data() argument
5095 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5096 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5097 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5098 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5099 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
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H A Dgfx_v9_0.c1930 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1933 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1941 uint32_t wave, uint32_t thread, in wave_read_regs() argument
1945 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
1955 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v9_0_read_wave_data() argument
1959 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
1960 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
1961 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
1962 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
1963 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
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H A Dgfx_v11_0.c995 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
998 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1003 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
1008 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
1016 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) in gfx_v11_0_read_wave_data() argument
1023 /* type 3 wave data */ in gfx_v11_0_read_wave_data()
1025 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v11_0_read_wave_data()
1026 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v11_0_read_wave_data()
1027 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v11_0_read_wave_data()
1028 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_L in gfx_v11_0_read_wave_data()
1043 gfx_v11_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst) gfx_v11_0_read_wave_sgprs() argument
1054 gfx_v11_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst) gfx_v11_0_read_wave_vgprs() argument
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H A Dgfx_v10_0.c4477 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
4480 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4485 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
4490 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4498 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v10_0_read_wave_data() argument
4508 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v10_0_read_wave_data()
4509 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v10_0_read_wave_data()
4510 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v10_0_read_wave_data()
4511 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v10_0_read_wave_data()
4512 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v10_0_read_wave_data()
[all …]
/linux/drivers/gpu/ipu-v3/
H A Dipu-dc.c120 int map, int wave, int glue, int sync, int stop) in dc_write_tmpl() argument
129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); in dc_write_tmpl()
132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); in dc_write_tmpl()
/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst103 This generates a high / low square wave. The count
112 which generates sine-like tones by low-pass filtering the square wave output.
253 bit 3 = Square wave interrupt enable
/linux/Documentation/driver-api/media/drivers/
H A Dvidtv.rst34 Elementary Stream, which in turn contains a SMPTE 302m encoded sine-wave.