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Searched refs:wait_reg_mem (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v12_1.c607 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; in mes_v12_1_misc_op()
608 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_1_misc_op()
609 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_1_misc_op()
610 misc_pkt.wait_reg_mem.reg_offset2 = 0; in mes_v12_1_misc_op()
613 &misc_pkt.wait_reg_mem.rrmt_opt1, in mes_v12_1_misc_op()
614 &misc_pkt.wait_reg_mem.reg_offset1); in mes_v12_1_misc_op()
618 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; in mes_v12_1_misc_op()
619 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_1_misc_op()
620 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_1_misc_op()
623 &misc_pkt.wait_reg_mem.rrmt_opt1, in mes_v12_1_misc_op()
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H A Dmes_v11_0.c921 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; in mes_v11_0_misc_op()
922 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()
923 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()
924 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()
925 misc_pkt.wait_reg_mem.reg_offset2 = 0; in mes_v11_0_misc_op()
929 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; in mes_v11_0_misc_op()
930 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()
931 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()
932 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()
933 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v11_0_misc_op()
H A Dmes_v12_0.c872 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; in mes_v12_0_misc_op()
873 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_0_misc_op()
874 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_0_misc_op()
875 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v12_0_misc_op()
876 misc_pkt.wait_reg_mem.reg_offset2 = 0; in mes_v12_0_misc_op()
880 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; in mes_v12_0_misc_op()
881 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_0_misc_op()
882 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_0_misc_op()
883 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v12_0_misc_op()
884 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v12_0_misc_op()
/linux/drivers/gpu/drm/radeon/
H A Dr600_cs.c833 struct radeon_cs_packet p3reloc, wait_reg_mem; in r600_cs_common_vline_parse() local
842 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx); in r600_cs_common_vline_parse()
847 if (wait_reg_mem.type != RADEON_PACKET_TYPE3 || in r600_cs_common_vline_parse()
848 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { in r600_cs_common_vline_parse()
853 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_common_vline_parse()
869 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { in r600_cs_common_vline_parse()
874 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { in r600_cs_common_vline_parse()
880 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); in r600_cs_common_vline_parse()
885 p->idx += wait_reg_mem.count + 2; in r600_cs_common_vline_parse()
/linux/drivers/gpu/drm/amd/include/
H A Dmes_v11_api_def.h716 struct WAIT_REG_MEM wait_reg_mem; member