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Searched refs:vpu (Results 1 – 25 of 89) sorted by relevance

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/linux/drivers/remoteproc/
H A Dingenic_rproc.c61 struct vpu { struct
71 struct vpu *vpu = rproc->priv; in ingenic_rproc_prepare() argument
75 ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_prepare()
77 dev_err(vpu->dev, "Unable to start clocks: %d\n", ret); in ingenic_rproc_prepare()
84 struct vpu *vpu = rproc->priv; in ingenic_rproc_unprepare() local
86 clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_unprepare()
93 struct vpu *vpu = rproc->priv; in ingenic_rproc_start() local
96 enable_irq(vpu->irq); in ingenic_rproc_start()
100 writel(ctrl, vpu->aux_base + REG_AUX_CTRL); in ingenic_rproc_start()
107 struct vpu *vpu = rproc->priv; in ingenic_rproc_stop() local
[all …]
/linux/drivers/media/platform/verisilicon/
H A Dhantro_drv.c62 static void hantro_job_finish_no_pm(struct hantro_dev *vpu, in hantro_job_finish_no_pm() argument
89 static void hantro_job_finish(struct hantro_dev *vpu, in hantro_job_finish() argument
93 pm_runtime_put_autosuspend(vpu->dev); in hantro_job_finish()
95 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); in hantro_job_finish()
97 hantro_job_finish_no_pm(vpu, ctx, result); in hantro_job_finish()
100 void hantro_irq_done(struct hantro_dev *vpu, in hantro_irq_done() argument
104 v4l2_m2m_get_curr_priv(vpu->m2m_dev); in hantro_irq_done()
111 if (cancel_delayed_work(&vpu->watchdog_work)) { in hantro_irq_done()
114 hantro_job_finish(vpu, ctx, result); in hantro_irq_done()
120 struct hantro_dev *vpu; in hantro_watchdog() local
[all …]
H A Drockchip_vpu2_hw_vp8_dec.c280 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
285 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
291 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
295 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
302 vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ); in cfg_lf()
306 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
308 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
319 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
323 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
329 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
[all …]
H A Drockchip_vpu2_hw_jpeg_enc.c35 static void rockchip_vpu2_set_src_img_ctrl(struct hantro_dev *vpu, in rockchip_vpu2_set_src_img_ctrl() argument
51 vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); in rockchip_vpu2_set_src_img_ctrl()
61 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET); in rockchip_vpu2_set_src_img_ctrl()
64 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); in rockchip_vpu2_set_src_img_ctrl()
67 static void rockchip_vpu2_jpeg_enc_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_jpeg_enc_set_buffers() argument
82 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) + in rockchip_vpu2_jpeg_enc_set_buffers()
85 vepu_write_relaxed(vpu, size_left, VEPU_REG_STR_BUF_LIMIT); in rockchip_vpu2_jpeg_enc_set_buffers()
89 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rockchip_vpu2_jpeg_enc_set_buffers()
93 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rockchip_vpu2_jpeg_enc_set_buffers()
94 vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1); in rockchip_vpu2_jpeg_enc_set_buffers()
[all …]
H A Dhantro_g1_vp8_dec.c139 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
144 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
150 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
154 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
161 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); in cfg_lf()
165 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
167 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
181 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
185 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
191 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
[all …]
H A Dhantro_h1_jpeg_enc.c18 static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu, in hantro_h1_set_src_img_ctrl() argument
37 vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); in hantro_h1_set_src_img_ctrl()
40 static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu, in hantro_h1_jpeg_enc_set_buffers() argument
55 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) + in hantro_h1_jpeg_enc_set_buffers()
58 vepu_write_relaxed(vpu, size_left, H1_REG_STR_BUF_LIMIT); in hantro_h1_jpeg_enc_set_buffers()
63 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
67 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
68 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
73 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
74 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
[all …]
H A Dhantro_g1_h264_dec.c28 struct hantro_dev *vpu = ctx->dev; in set_params() local
49 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
55 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
65 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
71 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
85 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); in set_params()
100 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); in set_params()
107 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); in set_params()
110 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
113 vdpu_write_relaxed(vpu, in set_params()
[all …]
H A Drockchip_vpu2_hw_mpeg2_dec.c83 rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_quantisation() argument
90 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE); in rockchip_vpu2_mpeg2_dec_set_quantisation()
94 rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_buffers() argument
114 vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
122 vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
139 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
140 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
142 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
[all …]
H A Drockchip_vpu2_hw_h264_dec.c199 struct hantro_dev *vpu = ctx->dev; in set_params() local
207 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in set_params()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in set_params()
216 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in set_params()
219 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in set_params()
227 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in set_params()
233 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in set_params()
248 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); in set_params()
253 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); in set_params()
256 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65)); in set_params()
[all …]
H A Dhantro_g1_mpeg2_dec.c81 hantro_g1_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in hantro_g1_mpeg2_dec_set_quantisation() argument
88 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, G1_REG_QTABLE_BASE); in hantro_g1_mpeg2_dec_set_quantisation()
92 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx, in hantro_g1_mpeg2_dec_set_buffers() argument
111 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
119 vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE); in hantro_g1_mpeg2_dec_set_buffers()
133 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
134 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
139 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
[all …]
H A Dhantro_g1.c16 struct hantro_dev *vpu = dev_id; in hantro_g1_irq() local
20 status = vdpu_read(vpu, G1_REG_INTERRUPT); in hantro_g1_irq()
24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
27 hantro_irq_done(vpu, state); in hantro_g1_irq()
34 struct hantro_dev *vpu = ctx->dev; in hantro_g1_reset() local
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
H A Dhantro_hevc.c77 struct hantro_dev *vpu = ctx->dev; in tile_buffer_reallocate() local
92 dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size, in tile_buffer_reallocate()
99 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in tile_buffer_reallocate()
106 dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size, in tile_buffer_reallocate()
113 hevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
121 hevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
129 hevc_dec->tile_bsd.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
142 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in tile_buffer_reallocate()
149 dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size, in tile_buffer_reallocate()
217 struct hantro_dev *vpu = ctx->dev; in hantro_hevc_dec_exit() local
[all …]
H A DMakefile3 obj-$(CONFIG_VIDEO_HANTRO) += hantro-vpu.o
5 hantro-vpu-y += \
24 hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \
27 hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \
30 hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \
40 hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \
43 hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) += \
H A Dhantro_vp9.c160 struct hantro_dev *vpu = ctx->dev; in hantro_vp9_dec_init() local
161 const struct hantro_variant *variant = vpu->variant; in hantro_vp9_dec_init()
178 max_width = vpu->variant->dec_fmts[i].frmsize.max_width; in hantro_vp9_dec_init()
179 max_height = vpu->variant->dec_fmts[i].frmsize.max_height; in hantro_vp9_dec_init()
185 tile_edge->cpu = dma_alloc_coherent(vpu->dev, size, &tile_edge->dma, GFP_KERNEL); in hantro_vp9_dec_init()
196 segment_map->cpu = dma_alloc_coherent(vpu->dev, size, &segment_map->dma, GFP_KERNEL); in hantro_vp9_dec_init()
209 misc->cpu = dma_alloc_coherent(vpu->dev, size, &misc->dma, GFP_KERNEL); in hantro_vp9_dec_init()
221 dma_free_coherent(vpu->dev, segment_map->size, segment_map->cpu, segment_map->dma); in hantro_vp9_dec_init()
224 dma_free_coherent(vpu->dev, tile_edge->size, tile_edge->cpu, tile_edge->dma); in hantro_vp9_dec_init()
231 struct hantro_dev *vpu = ctx->dev; in hantro_vp9_dec_exit() local
[all …]
H A Dstm32mp25_vpu_hw.c99 struct hantro_dev *vpu = dev_id; in stm32mp25_venc_irq() local
103 status = vepu_read(vpu, H1_REG_INTERRUPT); in stm32mp25_venc_irq()
107 vepu_write(vpu, H1_REG_INTERRUPT_BIT, H1_REG_INTERRUPT); in stm32mp25_venc_irq()
109 hantro_irq_done(vpu, state); in stm32mp25_venc_irq()
116 struct hantro_dev *vpu = ctx->dev; in stm32mp25_venc_reset() local
118 reset_control_reset(vpu->resets); in stm32mp25_venc_reset()
/linux/drivers/media/platform/mediatek/mdp/
H A Dmtk_mdp_vpu.c13 static inline struct mtk_mdp_ctx *vpu_to_ctx(struct mtk_mdp_vpu *vpu) in vpu_to_ctx() argument
15 return container_of(vpu, struct mtk_mdp_ctx, vpu); in vpu_to_ctx()
20 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_handle_init_ack() local
24 vpu->vsi = (struct mdp_process_vsi *) in mtk_mdp_vpu_handle_init_ack()
25 vpu_mapping_dm_addr(vpu->pdev, msg->vpu_inst_addr); in mtk_mdp_vpu_handle_init_ack()
26 vpu->inst_addr = msg->vpu_inst_addr; in mtk_mdp_vpu_handle_init_ack()
34 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_ipi_handler() local
38 vpu->failure = msg->status; in mtk_mdp_vpu_ipi_handler()
39 if (!vpu->failure) { in mtk_mdp_vpu_ipi_handler()
48 ctx = vpu_to_ctx(vpu); in mtk_mdp_vpu_ipi_handler()
[all …]
H A Dmtk_mdp_regs.c51 struct mdp_buffer *src_buf = &ctx->vpu.vsi->src_buffer; in mtk_mdp_hw_set_input_addr()
61 struct mdp_buffer *dst_buf = &ctx->vpu.vsi->dst_buffer; in mtk_mdp_hw_set_output_addr()
71 struct mdp_config *config = &ctx->vpu.vsi->src_config; in mtk_mdp_hw_set_in_size()
92 struct mdp_config *config = &ctx->vpu.vsi->src_config; in mtk_mdp_hw_set_in_image_format()
93 struct mdp_buffer *src_buf = &ctx->vpu.vsi->src_buffer; in mtk_mdp_hw_set_in_image_format()
107 struct mdp_config *config = &ctx->vpu.vsi->dst_config; in mtk_mdp_hw_set_out_size()
123 struct mdp_config *config = &ctx->vpu.vsi->dst_config; in mtk_mdp_hw_set_out_image_format()
124 struct mdp_buffer *dst_buf = &ctx->vpu.vsi->dst_buffer; in mtk_mdp_hw_set_out_image_format()
136 struct mdp_config_misc *misc = &ctx->vpu.vsi->misc; in mtk_mdp_hw_set_rotation()
145 struct mdp_config_misc *misc = &ctx->vpu.vsi->misc; in mtk_mdp_hw_set_global_alpha()
/linux/drivers/media/platform/amphion/
H A Dvpu_imx8q.c42 int vpu_imx8q_setup_dec(struct vpu_dev *vpu) in vpu_imx8q_setup_dec() argument
46 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f); in vpu_imx8q_setup_dec()
47 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff); in vpu_imx8q_setup_dec()
52 int vpu_imx8q_setup_enc(struct vpu_dev *vpu) in vpu_imx8q_setup_enc() argument
57 int vpu_imx8q_setup(struct vpu_dev *vpu) in vpu_imx8q_setup() argument
61 vpu_readl(vpu, offset + 0x108); in vpu_imx8q_setup()
63 vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1); in vpu_imx8q_setup()
64 vpu_writel(vpu, offset + 0x190, 0xffffffff); in vpu_imx8q_setup()
65 vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff); in vpu_imx8q_setup()
66 vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0xE); in vpu_imx8q_setup()
[all …]
/linux/drivers/media/platform/mediatek/vcodec/decoder/
H A Dvdec_vpu_if.h53 int vpu_dec_init(struct vdec_vpu_inst *vpu);
63 int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t *data, unsigned int len);
73 int vpu_dec_end(struct vdec_vpu_inst *vpu);
80 int vpu_dec_deinit(struct vdec_vpu_inst *vpu);
88 int vpu_dec_reset(struct vdec_vpu_inst *vpu);
96 int vpu_dec_core(struct vdec_vpu_inst *vpu);
106 int vpu_dec_core_end(struct vdec_vpu_inst *vpu);
116 int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data,
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp8_req_if.c103 struct vdec_vpu_inst vpu; member
125 vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); in vdec_vp8_slice_get_pic_info()
129 ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0]; in vdec_vp8_slice_get_pic_info()
130 ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1]; in vdec_vp8_slice_get_pic_info()
284 inst->vpu.id = SCP_IPI_VDEC_LAT; in vdec_vp8_slice_init()
285 inst->vpu.core_id = SCP_IPI_VDEC_CORE; in vdec_vp8_slice_init()
286 inst->vpu.ctx = ctx; in vdec_vp8_slice_init()
287 inst->vpu.codec_type = ctx->current_codec; in vdec_vp8_slice_init()
288 inst->vpu.capture_type = ctx->capture_fourcc; in vdec_vp8_slice_init()
290 err = vpu_dec_init(&inst->vpu); in vdec_vp8_slice_init()
[all …]
H A Dvdec_h264_req_multi_if.c242 struct vdec_vpu_inst vpu; member
444 vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); in vdec_h264_slice_get_pic_info()
448 ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0]; in vdec_h264_slice_get_pic_info()
449 ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1]; in vdec_h264_slice_get_pic_info()
584 struct vdec_vpu_inst *vpu = &inst->vpu; in vdec_h264_slice_core_decode_ext() local
595 err = vpu_dec_core(vpu); in vdec_h264_slice_core_decode_ext()
608 vpu_dec_core_end(vpu); in vdec_h264_slice_core_decode_ext()
636 struct vdec_vpu_inst *vpu = &inst->vpu; in vdec_h264_slice_core_decode() local
682 err = vpu_dec_core(vpu); in vdec_h264_slice_core_decode()
695 vpu_dec_core_end(vpu); in vdec_h264_slice_core_decode()
[all …]
H A Dvdec_h264_req_if.c89 struct vdec_vpu_inst vpu; member
282 inst->vpu.id = SCP_IPI_VDEC_H264; in vdec_h264_slice_init()
283 inst->vpu.ctx = ctx; in vdec_h264_slice_init()
285 err = vpu_dec_init(&inst->vpu); in vdec_h264_slice_init()
291 memcpy(&inst->vsi_ctx, inst->vpu.vsi, sizeof(inst->vsi_ctx)); in vdec_h264_slice_init()
311 vpu_dec_deinit(&inst->vpu); in vdec_h264_slice_init()
322 vpu_dec_deinit(&inst->vpu); in vdec_h264_slice_deinit()
335 struct vdec_vpu_inst *vpu = &inst->vpu; in vdec_h264_slice_decode() local
347 return vpu_dec_reset(vpu); in vdec_h264_slice_decode()
397 memcpy(inst->vpu.vsi, &inst->vsi_ctx, sizeof(inst->vsi_ctx)); in vdec_h264_slice_decode()
[all …]
H A Dvdec_h264_if.c130 struct vdec_vpu_inst vpu; member
279 inst->vpu.id = IPI_VDEC_H264; in vdec_h264_init()
280 inst->vpu.ctx = ctx; in vdec_h264_init()
282 err = vpu_dec_init(&inst->vpu); in vdec_h264_init()
288 inst->vsi = (struct vdec_h264_vsi *)inst->vpu.vsi; in vdec_h264_init()
299 vpu_dec_deinit(&inst->vpu); in vdec_h264_init()
310 vpu_dec_deinit(&inst->vpu); in vdec_h264_deinit()
333 struct vdec_vpu_inst *vpu = &inst->vpu; in vdec_h264_decode() local
350 return vpu_dec_reset(vpu); in vdec_h264_decode()
382 err = vpu_dec_start(vpu, data, 2); in vdec_h264_decode()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-vpu.dtsi7 vpu: vpu@2c000000 { label
42 vpu_core0: vpu-core@2d080000 {
44 compatible = "nxp,imx8q-vpu-decoder";
53 vpu_core1: vpu-core@2d090000 {
55 compatible = "nxp,imx8q-vpu-encoder";
64 vpu_core2: vpu-core@2d0a0000 {
66 compatible = "nxp,imx8q-vpu-encoder";
/linux/drivers/media/platform/mediatek/vcodec/encoder/
H A Dvenc_vpu_if.h40 int vpu_enc_init(struct venc_vpu_inst *vpu);
41 int vpu_enc_set_param(struct venc_vpu_inst *vpu,
44 int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode,
48 int vpu_enc_deinit(struct venc_vpu_inst *vpu);

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