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Searched refs:vm_manager (Results 1 – 25 of 35) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vm.c524 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
525 adev->vm_manager.vm_pte_num_scheds, NULL); in amdgpu_vm_init_entities()
530 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
531 adev->vm_manager.vm_pte_num_scheds, NULL); in amdgpu_vm_init_entities()
746 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
783 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_flush()
1354 vram_base = bo_adev->vm_manager.vram_base_offset; in amdgpu_vm_bo_update()
1446 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); in amdgpu_vm_update_prt_state()
1447 enable = !!atomic_read(&adev->vm_manager.num_prt_users); in amdgpu_vm_update_prt_state()
1449 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); in amdgpu_vm_update_prt_state()
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H A Damdgpu_vm.h55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
170 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \
490 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib…
491 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->wri…
492 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_fu…
H A Dgfxhub_v2_0.c293 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
310 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
323 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
326 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
H A Dgfxhub_v1_0.c257 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
258 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
303 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
306 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
H A Dmmhub_v2_0.c358 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
376 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
389 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
392 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
H A Dmmhub_v2_3.c282 adev->vm_manager.num_level); in mmhub_v2_3_setup_vmid_config()
300 adev->vm_manager.block_size - 9); in mmhub_v2_3_setup_vmid_config()
313 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
316 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
H A Dgfxhub_v2_1.c305 adev->vm_manager.num_level); in gfxhub_v2_1_setup_vmid_config()
322 adev->vm_manager.block_size - 9); in gfxhub_v2_1_setup_vmid_config()
335 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
338 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
H A Dgfxhub_v1_2.c336 num_level = adev->vm_manager.num_level; in gfxhub_v1_2_xcc_setup_vmid_config()
337 block_size = adev->vm_manager.block_size; in gfxhub_v1_2_xcc_setup_vmid_config()
391 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_2_xcc_setup_vmid_config()
395 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_2_xcc_setup_vmid_config()
H A Dmmhub_v1_0.c285 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
286 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
327 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
330 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
H A Dgfxhub_v12_1.c417 num_level = adev->vm_manager.num_level; in gfxhub_v12_1_xcc_setup_vmid_config()
418 block_size = adev->vm_manager.block_size; in gfxhub_v12_1_xcc_setup_vmid_config()
462 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v12_1_xcc_setup_vmid_config()
466 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v12_1_xcc_setup_vmid_config()
H A Damdgpu_amdkfd.c183 ((1 << adev->vm_manager.first_kfd_vmid) - 1), in amdgpu_amdkfd_device_init()
186 .gpuvm_size = min(adev->vm_manager.max_pfn in amdgpu_amdkfd_device_init()
771 return vmid >= adev->vm_manager.first_kfd_vmid; in amdgpu_amdkfd_is_kfd_vmid()
H A Dgmc_v11_0.c669 adev->vm_manager.vram_base_offset = 0; in gmc_v11_0_vram_gtt_location()
671 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_vram_gtt_location()
853 adev->vm_manager.first_kfd_vmid = adev->gfx.disable_kq ? 1 : 8; in gmc_v11_0_sw_init()
H A Damdgpu_gmc.c1161 vram_addr = adev->vm_manager.vram_base_offset; in amdgpu_gmc_init_pdb0()
1192 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; in amdgpu_gmc_vram_mc2pa()
1451 adev->vm_manager.vram_base_offset) >> in amdgpu_gmc_get_nps_memranges()
1455 adev->vm_manager.vram_base_offset) >> in amdgpu_gmc_get_nps_memranges()
H A Dgmc_v12_1.c554 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v12_1_get_vm_pde()
H A Dmes_userqueue.c127 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; in mes_userq_map()
H A Damdgpu_dev_coredump.c423 fault_info = &coredump->adev->vm_manager.fault_info; in amdgpu_devcoredump_format()
H A Damdgpu_device.c3792 adev->vm_manager.vm_pte_funcs = NULL; in amdgpu_device_init()
3793 adev->vm_manager.vm_pte_num_scheds = 0; in amdgpu_device_init()
4657 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in amdgpu_virt_resume()
4658 adev->vm_manager.vram_base_offset += in amdgpu_virt_resume()
H A Damdgpu.h683 struct amdgpu_vm_manager vm_manager; member
H A Damdgpu_mes.c127 reserved_vmid_mask = (u32)((1UL << adev->vm_manager.first_kfd_vmid) - 1); in amdgpu_mes_init()
H A Damdgpu_gem.c873 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; in amdgpu_gem_va_ioctl()
H A Damdgpu_ttm.c280 u64 pa = mm_cur->start + adev->vm_manager.vram_base_offset; in amdgpu_ttm_map_buffer()
2762 (adev->vm_manager.concurrent_flush && in amdgpu_sdma_set_buffer_funcs_scheds()
H A Dgfx_v9_0.c2609 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { in gfx_v9_0_init_compute_vmid()
2620 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { in gfx_v9_0_init_compute_vmid()
2685 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { in gfx_v9_0_constants_init()
4929 adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID); in gfx_v9_0_late_init()
4932 adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID); in gfx_v9_0_late_init()
/linux/drivers/gpu/drm/radeon/
H A Dradeon_vm.c62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
186 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
193 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
194 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
213 return rdev->vm_manager.active[choices[i]]; in radeon_vm_grab_id()
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H A Dni.c1300 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1302 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1337 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
2481 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2486 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2488 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
H A Dradeon_cs.c367 !p->rdev->vm_manager.enabled) { in radeon_cs_parser_init()

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