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Searched refs:vm_manager (Results 1 – 25 of 42) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vm.c531 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
532 adev->vm_manager.vm_pte_num_scheds, NULL); in amdgpu_vm_init_entities()
537 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
538 adev->vm_manager.vm_pte_num_scheds, NULL); in amdgpu_vm_init_entities()
742 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
777 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_flush()
1329 vram_base = bo_adev->vm_manager.vram_base_offset; in amdgpu_vm_bo_update()
1415 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); in amdgpu_vm_update_prt_state()
1416 enable = !!atomic_read(&adev->vm_manager.num_prt_users); in amdgpu_vm_update_prt_state()
1418 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); in amdgpu_vm_update_prt_state()
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H A Damdgpu_ids.c203 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
214 struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ? in amdgpu_vmid_grab_idle()
269 (!adev->vm_manager.concurrent_flush && needs_flush)) { in amdgpu_vmid_grab_reserved()
275 if (adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_reserved()
318 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
344 if (needs_flush && !adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_used()
379 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab()
465 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_alloc_reserved()
498 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_free_reserved()
522 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_reset()
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H A Dgfxhub_v12_0.c175 + adev->vm_manager.vram_base_offset; in gfxhub_v12_0_init_system_aperture_regs()
308 adev->vm_manager.num_level); in gfxhub_v12_0_setup_vmid_config()
325 adev->vm_manager.block_size - 9); in gfxhub_v12_0_setup_vmid_config()
338 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v12_0_setup_vmid_config()
341 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v12_0_setup_vmid_config()
H A Damdgpu_vm.h55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
170 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \
492 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib…
493 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->wri…
494 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_fu…
H A Dmmhub_v4_1_0.c185 adev->vm_manager.vram_base_offset; in mmhub_v4_1_0_init_system_aperture_regs()
322 adev->vm_manager.num_level); in mmhub_v4_1_0_setup_vmid_config()
340 adev->vm_manager.block_size - 9); in mmhub_v4_1_0_setup_vmid_config()
353 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v4_1_0_setup_vmid_config()
356 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v4_1_0_setup_vmid_config()
H A Dgfxhub_v3_0_3.c305 adev->vm_manager.num_level); in gfxhub_v3_0_3_setup_vmid_config()
322 adev->vm_manager.block_size - 9); in gfxhub_v3_0_3_setup_vmid_config()
335 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()
338 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()
H A Dgfxhub_v2_0.c293 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
310 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
323 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
326 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
H A Dgfxhub_v11_5_0.c303 adev->vm_manager.num_level); in gfxhub_v11_5_0_setup_vmid_config()
320 adev->vm_manager.block_size - 9); in gfxhub_v11_5_0_setup_vmid_config()
333 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v11_5_0_setup_vmid_config()
336 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v11_5_0_setup_vmid_config()
H A Dmmhub_v3_0_2.c321 adev->vm_manager.num_level); in mmhub_v3_0_2_setup_vmid_config()
339 adev->vm_manager.block_size - 9); in mmhub_v3_0_2_setup_vmid_config()
352 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
355 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
H A Dgfxhub_v3_0.c300 adev->vm_manager.num_level); in gfxhub_v3_0_setup_vmid_config()
317 adev->vm_manager.block_size - 9); in gfxhub_v3_0_setup_vmid_config()
330 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
333 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
H A Damdgpu_gmc.h36 #define AMDGPU_GMC_HOLE_START (adev->vm_manager.max_level == 4 ?\
38 #define AMDGPU_GMC_HOLE_END (adev->vm_manager.max_level == 4 ?\
48 #define AMDGPU_GMC_HOLE_MASK (adev->vm_manager.max_level == 4 ?\
H A Dmmhub_v3_0_1.c323 adev->vm_manager.num_level); in mmhub_v3_0_1_setup_vmid_config()
341 adev->vm_manager.block_size - 9); in mmhub_v3_0_1_setup_vmid_config()
354 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()
357 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()
H A Dmmhub_v3_0.c329 adev->vm_manager.num_level); in mmhub_v3_0_setup_vmid_config()
347 adev->vm_manager.block_size - 9); in mmhub_v3_0_setup_vmid_config()
360 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()
363 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()
H A Dmmhub_v2_3.c291 adev->vm_manager.num_level); in mmhub_v2_3_setup_vmid_config()
309 adev->vm_manager.block_size - 9); in mmhub_v2_3_setup_vmid_config()
322 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
325 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
H A Dmmhub_v2_0.c373 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
391 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
404 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
407 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
H A Dgmc_v7_0.c578 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
647 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
676 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
694 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1054 adev->vm_manager.first_kfd_vmid = 8; in gmc_v7_0_sw_init()
1062 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1064 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
H A Dgmc_v8_0.c795 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
865 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
909 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
934 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
1169 adev->vm_manager.first_kfd_vmid = 8; in gmc_v8_0_sw_init()
1177 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1179 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
H A Dmmhub_v1_0.c285 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
286 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
327 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
330 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
H A Dgmc_v9_0.c1652 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v9_0_vram_gtt_location()
1655 adev->vm_manager.vram_base_offset += in gmc_v9_0_vram_gtt_location()
1891 adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1910 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1919 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1931 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
2015 adev->vm_manager.first_kfd_vmid = in gmc_v9_0_sw_init()
H A Dmmhub_v4_2_0.c459 adev->vm_manager.num_level); in mmhub_v4_2_0_mid_setup_vmid_config()
477 adev->vm_manager.block_size - 9); in mmhub_v4_2_0_mid_setup_vmid_config()
490 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v4_2_0_mid_setup_vmid_config()
493 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v4_2_0_mid_setup_vmid_config()
H A Damdgpu_amdkfd.c179 ((1 << adev->vm_manager.first_kfd_vmid) - 1), in amdgpu_amdkfd_device_init()
182 .gpuvm_size = min(adev->vm_manager.max_pfn in amdgpu_amdkfd_device_init()
729 return vmid >= adev->vm_manager.first_kfd_vmid; in amdgpu_amdkfd_is_kfd_vmid()
H A Damdgpu_gmc.c1146 vram_addr = adev->vm_manager.vram_base_offset; in amdgpu_gmc_init_pdb0()
1177 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; in amdgpu_gmc_vram_mc2pa()
1436 adev->vm_manager.vram_base_offset) >> in amdgpu_gmc_get_nps_memranges()
1440 adev->vm_manager.vram_base_offset) >> in amdgpu_gmc_get_nps_memranges()
H A Dsdma_v5_0.c2066 if (adev->vm_manager.vm_pte_funcs == NULL) { in sdma_v5_0_set_vm_pte_funcs()
2067 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; in sdma_v5_0_set_vm_pte_funcs()
2069 adev->vm_manager.vm_pte_scheds[i] = in sdma_v5_0_set_vm_pte_funcs()
2072 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_0_set_vm_pte_funcs()
/linux/drivers/gpu/drm/radeon/
H A Dradeon_vm.c62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
186 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
193 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
194 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
213 return rdev->vm_manager.active[choices[i]]; in radeon_vm_grab_id()
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H A Dni.c1300 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1302 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1337 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
2481 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2486 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2488 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()

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