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Searched refs:val0 (Results 1 – 18 of 18) sorted by relevance

/linux/sound/i2c/other/
H A Dpt2258.c98 int val0, val1; in pt2258_stereo_volume_put() local
100 val0 = 79 - ucontrol->value.integer.value[0]; in pt2258_stereo_volume_put()
102 if (val0 < 0 || val0 > 79 || val1 < 0 || val1 > 79) in pt2258_stereo_volume_put()
104 if (val0 == pt->volume[base] && val1 == pt->volume[base + 1]) in pt2258_stereo_volume_put()
107 pt->volume[base] = val0; in pt2258_stereo_volume_put()
108 bytes[0] = pt2258_channel_code[2 * base] | (val0 / 10); in pt2258_stereo_volume_put()
109 bytes[1] = pt2258_channel_code[2 * base + 1] | (val0 % 10); in pt2258_stereo_volume_put()
/linux/samples/rust/
H A Drust_dma.rs96 let val0 = kernel::dma_read!(self.ca[i].h); in drop() localVariable
98 assert!(val0.is_ok()); in drop()
101 if let Ok(val0) = val0 { in drop()
102 assert_eq!(val0, value.0); in drop()
/linux/drivers/iio/common/hid-sensors/
H A Dhid-sensor-attributes.c359 static void adjust_exponent_nano(int *val0, int *val1, int scale0, in adjust_exponent_nano() argument
369 *val0 = scale0 * int_pow(10, exp); in adjust_exponent_nano()
381 *val0 += res; in adjust_exponent_nano()
386 *val0 = *val1 = 0; in adjust_exponent_nano()
390 *val0 = scale0 / divisor; in adjust_exponent_nano()
401 *val0 = scale0; in adjust_exponent_nano()
408 int *val0, int *val1) in hid_sensor_format_scale() argument
413 *val0 = 1; in hid_sensor_format_scale()
421 adjust_exponent_nano(val0, val1, in hid_sensor_format_scale()
563 int val0, val1; in hid_sensor_parse_common_attributes() local
[all …]
/linux/drivers/soc/rockchip/
H A Dio-domain.c90 u32 val0, val1; in rk3568_iodomain_write() local
98 val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); in rk3568_iodomain_write()
102 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0); in rk3568_iodomain_write()
114 val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); in rk3568_iodomain_write()
117 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL0, val0); in rk3568_iodomain_write()
/linux/drivers/net/dsa/microchip/
H A Dksz9477_acl.c338 u8 vale, valf, val0; in ksz9477_acl_update_linkage() local
341 val0 = entry[KSZ9477_ACL_PORT_ACCESS_0]; in ksz9477_acl_update_linkage()
355 if (val0 != old_idx) { in ksz9477_acl_update_linkage()
357 old_idx, val0); in ksz9477_acl_update_linkage()
361 val0 = new_idx; in ksz9477_acl_update_linkage()
378 entry[KSZ9477_ACL_PORT_ACCESS_0] = val0; in ksz9477_acl_update_linkage()
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dpm3393.c420 t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
423 (mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
437 u32 val0, val1, val2, val3; in pm3393_update_statistics() local
444 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0); in pm3393_update_statistics()
448 ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) | in pm3393_update_statistics()
/linux/drivers/edac/
H A Dversal_edac.c819 static void xddr_inject_data_ue_store(struct mem_ctl_info *mci, u32 val0, u32 val1) in xddr_inject_data_ue_store() argument
823 writel(val0, priv->ddrmc_baseaddr + ECCW0_FLIP0_OFFSET); in xddr_inject_data_ue_store()
824 writel(val0, priv->ddrmc_baseaddr + ECCW0_FLIP1_OFFSET); in xddr_inject_data_ue_store()
855 u32 val0 = 0, val1 = 0; in inject_data_ue_store() local
880 val0 = BIT(ue0); in inject_data_ue_store()
887 val0 |= BIT(ue1); in inject_data_ue_store()
899 xddr_inject_data_ue_store(mci, val0, val1); in inject_data_ue_store()
/linux/drivers/misc/sgi-gru/
H A Dgrulib.h97 int val0; member
H A Dgrufault.c875 if (req.val0 < -1 || req.val0 >= GRU_CHIPLETS_PER_HUB || in gru_set_context_option()
881 gts->ts_user_chiplet_id = req.val0; in gru_set_context_option()
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h178 u32 val0; member
183 { .val0 = _base, .val1 = _type, .registers = _array, \
301 .val0 = _sel_reg, .val1 = _sel_val }
H A Da6xx_gpu_state.c1021 regs->registers[i] - (regs->val0 >> 2); in a6xx_get_crashdumper_hlsq_registers()
1060 if (regs->val0) in a6xx_get_crashdumper_registers()
1061 in += CRASHDUMP_WRITE(in, regs->val0, regs->val1); in a6xx_get_crashdumper_registers()
/linux/drivers/media/usb/gspca/
H A Dov519.c2914 unsigned char val0, val1; in ov51x_upload_quan_tables() local
2930 val0 = *pYTable++; in ov51x_upload_quan_tables()
2932 val0 &= 0x0f; in ov51x_upload_quan_tables()
2934 val0 |= val1 << 4; in ov51x_upload_quan_tables()
2935 reg_w(sd, reg, val0); in ov51x_upload_quan_tables()
2937 val0 = *pUVTable++; in ov51x_upload_quan_tables()
2939 val0 &= 0x0f; in ov51x_upload_quan_tables()
2941 val0 |= val1 << 4; in ov51x_upload_quan_tables()
2942 reg_w(sd, reg + size, val0); in ov51x_upload_quan_tables()
/linux/include/linux/
H A Dhid-sensor-hub.h274 int *val0, int *val1);
/linux/drivers/thunderbolt/
H A Dicm.c1880 u32 val0, val1; in icm_reset_phy_port() local
1898 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1905 state0 = val0 & PHY_PORT_CS1_LINK_STATE_MASK; in icm_reset_phy_port()
1914 val0 |= PHY_PORT_CS1_LINK_DISABLE; in icm_reset_phy_port()
1915 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1927 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1934 val0 &= ~PHY_PORT_CS1_LINK_DISABLE; in icm_reset_phy_port()
1935 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
/linux/tools/testing/selftests/arm64/abi/
H A Dhwcap.c163 register u64 val0 asm ("x1") = 5; in lse128_sigill()
168 : "+r" (memp), "+r" (val0), "+r" (val1) in lse128_sigill()
/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c372 static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max) in pll_is_valid() argument
374 return (val0 >= (val1 * min) && val0 <= (val1 * max)); in pll_is_valid()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ring.h470 uint32_t reg0, uint32_t val0,
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-sriox-defs.h446 uint64_t val0:1; member
470 uint64_t val0:1;