| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_transform.c | 122 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
133 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in setup_scaling_configuration()
156 if (data->taps.h_taps + data->taps.v_taps <= 2) { in dce60_setup_scaling_configuration()
169 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in dce60_setup_scaling_configuration()
307 dc_fixpt_from_int(data->taps.v_taps + 1)), in calculate_inits()
336 dc_fixpt_from_int(data->taps.v_taps + 1)), in dce60_calculate_inits()
443 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce_transform_set_scaler()
453 data->taps.v_taps, in dce_transform_set_scaler()
458 data->taps.v_taps, in dce_transform_set_scaler()
530 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, dat in dce60_transform_set_scaler()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 226 if (in_taps->v_taps == 0) { in dpp201_get_optimal_number_of_taps()
228 scl_data->taps.v_taps = 8; in dpp201_get_optimal_number_of_taps()
230 scl_data->taps.v_taps = 4; in dpp201_get_optimal_number_of_taps()
232 scl_data->taps.v_taps = in_taps->v_taps; in dpp201_get_optimal_number_of_taps()
255 scl_data->taps.v_taps = 1; in dpp201_get_optimal_number_of_taps()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_dscl.c | 298 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 in dpp1_dscl_set_scl_filter()
300 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp1_dscl_set_scl_filter()
319 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter()
344 dpp, scl_data->taps.v_taps, in dpp1_dscl_set_scl_filter()
463 int vtaps = scl_data->taps.v_taps; in dpp1_dscl_find_lb_memory_config()
689 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, in dpp1_dscl_set_scaler_manual_scale()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 429 plane->composition.scaler_info.plane0.v_taps = 1; in populate_dml21_dummy_plane_cfg()
431 plane->composition.scaler_info.plane1.v_taps = 0; in populate_dml21_surface_config_from_plane_state()
569 if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) || in populate_dml21_plane_config_from_plane_state()
599 if (!scaler_data->taps.v_taps) { in populate_dml21_plane_config_from_plane_state()
600 plane->composition.scaler_info.plane0.v_taps = 1; in populate_dml21_plane_config_from_plane_state()
601 plane->composition.scaler_info.plane1.v_taps = 1; in populate_dml21_plane_config_from_plane_state()
603 plane->composition.scaler_info.plane0.v_taps = scaler_data->taps.v_taps; in populate_dml21_plane_config_from_plane_state()
604 plane->composition.scaler_info.plane1.v_taps = scaler_data->taps.v_taps_c; in populate_dml21_plane_config_from_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_transform_v.c | 167 set_reg_field_value(value, data->taps.v_taps - 1, in setup_scaling_configuration()
176 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
562 coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert); in dce110_xfmv_set_scaler()
574 data->taps.v_taps, in dce110_xfmv_set_scaler()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.c | 460 if (in_taps->v_taps == 0) { in dpp3_get_optimal_number_of_taps()
462 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
464 scl_data->taps.v_taps = 4; in dpp3_get_optimal_number_of_taps()
466 scl_data->taps.v_taps = in_taps->v_taps; in dpp3_get_optimal_number_of_taps()
520 if (scl_data->taps.v_taps > max_taps_y) in dpp3_get_optimal_number_of_taps()
521 scl_data->taps.v_taps = max_taps_y; in dpp3_get_optimal_number_of_taps()
532 scl_data->taps.v_taps = 1; in dpp3_get_optimal_number_of_taps()
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| /linux/drivers/gpu/drm/amd/display/dc/sspl/ |
| H A D | dc_spl_isharp_filters.c | 553 SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(data->taps.v_taps)); in SPL_NAMESPACE()
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| /linux/drivers/gpu/drm/amd/display/dc/basics/ |
| H A D | dce_calcs.c | 382 data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); in calculate_bandwidth()
383 data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); in calculate_bandwidth()
435 data->v_taps[i] = bw_int_to_fixed(1); in calculate_bandwidth()
544 if (bw_mtn(data->vsr[i], data->v_taps[i])) { in calculate_bandwidth()
580 if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) { in calculate_bandwidth()
803 data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i]), data->vsr[i]), bw_mul(bw_mul(bw_int_to_fixed(data->interlace_mode[i]), bw_frc_to_fixed(5, 10)), data->vsr[i]))), bw_int_to_fixed(2)), bw_int_to_fixed(1)); in calculate_bandwidth()
819 else if ((((dceip->underlay_downscale_prefetch_enabled == 1 && surface_type[i] != bw_def_graphics) || surface_type[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed(1))))))) { in calculate_bandwidth()
1253 data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i])); in calculate_bandwidth()
1256 data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1)))); in calculate_bandwidth()
1311 if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1 && (bw_equ(data->vsr[i], bw_int_to_fixed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[ in calculate_bandwidth()
[all...] |
| H A D | calcs_logger.h | 431 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_taps[%d]:%d", i, bw_fixed_to_int(data->v_taps[i])); in print_bw_calcs_data()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dwb_scl.c | 807 uint32_t v_taps_luma = num_taps.v_taps; in dwb_program_vert_scalar()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | dce_calcs.h | 397 struct bw_fixed v_taps[maximum_number_of_surfaces]; member
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_hw_types.h | 731 uint32_t v_taps;
718 uint32_t v_taps; global() member
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| H A D | dc.h | 3060 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */
2996 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */ global() member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 6788 double v_taps = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() local
6789 double v_taps_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6794 s->LBLatencyHidingSourceLinesY[k] = (unsigned int)(math_min2((double)p->MaxLineBufferLines, math_floor2((double)p->LineBufferSize / LBBitPerPixel / ((double)p->SwathWidthY[k] / math_max2(h_ratio, 1.0)), 1)) - (v_taps - 1)); in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6802 DML_LOG_VERBOSE("DML::%s: k=%u, VTaps = %f\n", __func__, k, v_taps); in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
7443 myPipe->VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps; in dml_core_ms_prefetch_check()
7444 myPipe->VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps; in dml_core_ms_prefetch_check()
8035 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps != 1.0)) { in dml_core_mode_support()
8037 } else if (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps < 1.0 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps > 8. in dml_core_mode_support()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
1014 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; in dcn_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1371 data->taps.v_taps, in calculate_inits_and_viewports()
1628 if (res && (pipe_ctx->plane_res.scl_data.taps.v_taps != temp.v_taps || in resource_build_scaling_params()
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| H A D | dc.c | 6876 state->dpp[i].v_taps = dscl_data->taps.v_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back in dc_capture_register_software_state()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm.c | 10675 wb_info->dwb_params.scaler_taps.v_taps = 1; in dm_set_writeback()
|