| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/ |
| H A D | dml2_pmo_dcn6_stage_optimizers.c | 133 *blackout_us = pmo->utm_soc_bb->power_management_parameters.dram_clk_change_blackout_us; in dcn6_get_params_for_pstate_type()
138 *blackout_us = pmo->utm_soc_bb->power_management_parameters.fclk_change_blackout_us; in dcn6_get_params_for_pstate_type()
144 pmo->utm_soc_bb->power_management_parameters.g7_ppt_blackout_us, in dcn6_get_params_for_pstate_type()
145 pmo->utm_soc_bb->power_management_parameters.g7_temperature_read_blackout_us); in dcn6_get_params_for_pstate_type()
152 pmo->utm_soc_bb->power_management_parameters.g7_ppt_blackout_us, in dcn6_get_params_for_pstate_type()
153 pmo->utm_soc_bb->power_management_parameters.g7_temperature_read_blackout_us); in dcn6_get_params_for_pstate_type()
1186 …REQUIRED_RESERVED_TIME = (int)pmo->utm_soc_bb->power_management_parameters.dram_clk_change_blackou… in dml2_pmo_dcn6_stage_optimizer_uclk_pstate_test_permissibility()
1612 const struct dml2_utm_soc_bb *utm_soc_bb = stage->pmo->utm_soc_bb; in dml2_pmo_dcn6_stage_optimizer_vmin_dcfclk_init() local
1616 utm_soc_bb->vmin_limit.dcfclk_khz * utm_soc_bb->return_bus_width_bytes; in dml2_pmo_dcn6_stage_optimizer_vmin_dcfclk_init()
1624 const struct dml2_utm_soc_bb *utm_soc_bb = stage->pmo->utm_soc_bb; in dml2_pmo_dcn6_stage_optimizer_vmin_dcfclk_optimize_next() local
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn5_funcs_mode_programming.c | 14 const struct dml2_utm_soc_bb *utm_soc_bb = in_out_params->utm_soc_bb; in dcn5_mode_programming() local
15 const struct dml2_sop_table *sop_table = &in_out_params->utm_soc_bb->sop_table; in dcn5_mode_programming()
428 utm_soc_bb->max_outstanding_reqs, in dcn5_mode_programming()
477 utm_soc_bb->max_outstanding_reqs, in dcn5_mode_programming()
496 utm_soc_bb->writeback_base_latency_us in dcn5_mode_programming()
533 calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us[k] = utm_soc_bb->power_management_parameters.dram_clk_change_blackout_us; in dcn5_mode_programming()
638 utm_soc_bb->power_management_parameters.g7_ppt_blackout_us, in dcn5_mode_programming()
1079 s->mmSOCParameters.WritebackLatency = utm_soc_bb->writeback_base_latency_us; in dcn5_mode_programming()
1080 s->mmSOCParameters.DRAMClockChangeLatency = utm_soc_bb in dcn5_mode_programming()
1600 const struct dml2_utm_soc_bb *utm_soc_bb = core->utm_soc_bb; dcn5_pack_mode_programming_params() local
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| H A D | dml2_core_dcn6_calcs_dchub.c | 735 const struct dml2_utm_soc_bb *utm_soc_bb) in dcn6_rq_dlg_get_dlg_reg()
756 l->refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : utm_soc_bb->dchub_refclk_mhz; in dcn6_rq_dlg_get_dlg_reg()
779 DML_LOG_VERBOSE("DML_DLG: %s: soc.refclk_mhz = %u\n", __func__, utm_soc_bb->dchub_refclk_mhz); in dcn6_rq_dlg_get_dlg_reg()
1059 static void dcn6_rq_dlg_get_wm_regs(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, const struct dml2_utm_soc_bb *utm_soc_bb, struct dml2_dchub_watermark_regs *wm_regs) in dcn6_calculate_pstate_support_method()
1061 double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : utm_soc_bb->dchub_refclk_mhz; in dcn6_calculate_pstate_support_method()
1084 const struct dml2_utm_soc_bb *utm_soc_bb, in dcn6_calculate_watermarks_and_dram_speed_change_support()
1088 dcn6_rq_dlg_get_dlg_reg(s, &out->dlg_regs, &out->ttu_regs, display_cfg, mode_lib, pipe_index, utm_soc_bb); in dcn6_calculate_watermarks_and_dram_speed_change_support()
1688 void dcn6_get_watermarks(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, const struct dml2_utm_soc_bb *utm_soc_bb, struct dml2_dchub_watermark_regs *out) in dcn6_calculate_pstate_schedule_windows()
1690 dcn6_rq_dlg_get_wm_regs(display_cfg, mode_lib, utm_soc_bb, out); in dcn6_calculate_pstate_schedule_windows()
683 dcn6_rq_dlg_get_dlg_reg(struct dml2_core_internal_scratch * s,struct dml2_display_dlg_regs * disp_dlg_regs,struct dml2_display_ttu_regs * disp_ttu_regs,const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,const unsigned int pipe_idx,const struct dml2_utm_soc_bb * utm_soc_bb) dcn6_rq_dlg_get_dlg_reg() argument
1007 dcn6_rq_dlg_get_wm_regs(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,const struct dml2_utm_soc_bb * utm_soc_bb,struct dml2_dchub_watermark_regs * wm_regs) dcn6_rq_dlg_get_wm_regs() argument
1032 dcn6_get_pipe_regs(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,struct dml2_dchub_per_pipe_register_set * out,int pipe_index,const struct dml2_utm_soc_bb * utm_soc_bb,struct dml2_core_internal_scratch * s) dcn6_get_pipe_regs() argument
1636 dcn6_get_watermarks(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,const struct dml2_utm_soc_bb * utm_soc_bb,struct dml2_dchub_watermark_regs * out) dcn6_get_watermarks() argument
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| H A D | dml2_core_dcn5_calcs_dchub.c | 5344 static void dcn5_rq_dlg_get_wm_regs(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, const struct dml2_utm_soc_bb *utm_soc_bb, struct dml2_dchub_watermark_regs *wm_regs) in dcn5_rq_dlg_get_wm_regs()
5346 double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : utm_soc_bb->dchub_refclk_mhz; in dcn5_rq_dlg_get_wm_regs()
5522 const struct dml2_utm_soc_bb *utm_soc_bb) in dcn5_rq_dlg_get_dlg_reg()
5542 l->refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : utm_soc_bb->dchub_refclk_mhz; in dcn5_rq_dlg_get_dlg_reg()
5565 DML_LOG_VERBOSE("DML_DLG: %s: soc.refclk_mhz = %u\n", __func__, utm_soc_bb->dchub_refclk_mhz); in dcn5_rq_dlg_get_dlg_reg()
5833 static void dcn5_rq_dlg_get_arb_params(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, const struct dml2_utm_soc_bb *utm_soc_bb, struct dml2_display_arb_regs *arb_param) in dcn5_rq_dlg_get_arb_params()
5835 double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : utm_soc_bb->dchub_refclk_mhz; in dcn5_rq_dlg_get_arb_params()
5837 arb_param->max_req_outstanding = utm_soc_bb->max_outstanding_reqs; in dcn5_rq_dlg_get_arb_params()
5838 arb_param->min_req_outstanding = utm_soc_bb->max_outstanding_reqs; // turn off the sat level feature if this set to max in dcn5_rq_dlg_get_arb_params()
5839 arb_param->sdpif_request_rate_limit = (3 * mode_lib->ip.words_per_channel * utm_soc_bb in dcn5_rq_dlg_get_arb_params()
5340 dcn5_rq_dlg_get_wm_regs(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,const struct dml2_utm_soc_bb * utm_soc_bb,struct dml2_dchub_watermark_regs * wm_regs) dcn5_rq_dlg_get_wm_regs() argument
5518 dcn5_rq_dlg_get_dlg_reg(struct dml2_core_internal_scratch * s,struct dml2_display_dlg_regs * disp_dlg_regs,struct dml2_display_ttu_regs * disp_ttu_regs,const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,const unsigned int pipe_idx,const struct dml2_utm_soc_bb * utm_soc_bb) dcn5_rq_dlg_get_dlg_reg() argument
5829 dcn5_rq_dlg_get_arb_params(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,const struct dml2_utm_soc_bb * utm_soc_bb,struct dml2_display_arb_regs * arb_param) dcn5_rq_dlg_get_arb_params() argument
5853 dcn5_get_watermarks(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,const struct dml2_utm_soc_bb * utm_soc_bb,struct dml2_dchub_watermark_regs * out) dcn5_get_watermarks() argument
5858 dcn5_get_arb_params(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,const struct dml2_utm_soc_bb * utm_soc_bb,struct dml2_display_arb_regs * out) dcn5_get_arb_params() argument
5866 dcn5_get_pipe_regs(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,struct dml2_dchub_per_pipe_register_set * out,int pipe_index,const struct dml2_utm_soc_bb * utm_soc_bb,struct dml2_core_internal_scratch * s) dcn5_get_pipe_regs() argument
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| H A D | dml2_core_shared_types.h | 2499 const struct dml2_utm_soc_bb *utm_soc_bb;
2515 const struct dml2_utm_soc_bb *utm_soc_bb;
2490 const struct dml2_utm_soc_bb *utm_soc_bb; global() member
2506 const struct dml2_utm_soc_bb *utm_soc_bb; global() member
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