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Searched refs:update_state (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/
H A Ddcn351_hwseq.c39 struct pg_block_update *update_state) in dcn351_calc_blocks_to_gate() argument
43 dcn35_calc_blocks_to_gate(dc, context, update_state); in dcn351_calc_blocks_to_gate()
46 if (!update_state->pg_pipe_res_update[PG_HUBP][i] && in dcn351_calc_blocks_to_gate()
47 !update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn351_calc_blocks_to_gate()
49 update_state->pg_pipe_res_update[PG_HUBP][j] = false; in dcn351_calc_blocks_to_gate()
50 update_state->pg_pipe_res_update[PG_DPP][j] = false; in dcn351_calc_blocks_to_gate()
59 struct pg_block_update *update_state) in dcn351_calc_blocks_to_ungate() argument
63 dcn35_calc_blocks_to_ungate(dc, context, update_state); in dcn351_calc_blocks_to_ungate()
66 if (update_state->pg_pipe_res_update[PG_HUBP][i] && in dcn351_calc_blocks_to_ungate()
67 update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn351_calc_blocks_to_ungate()
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H A Ddcn351_hwseq.h33 struct pg_block_update *update_state);
35 struct pg_block_update *update_state);
37 struct pg_block_update *update_state);
39 struct pg_block_update *update_state);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c919 struct pg_block_update *update_state) in dcn35_calc_blocks_to_gate() argument
927 memset(update_state, 0, sizeof(struct pg_block_update)); in dcn35_calc_blocks_to_gate()
938 update_state->pg_res_update[PG_HPO] = true; in dcn35_calc_blocks_to_gate()
940 update_state->pg_res_update[PG_DWB] = true; in dcn35_calc_blocks_to_gate()
946 update_state->pg_pipe_res_update[j][i] = true; in dcn35_calc_blocks_to_gate()
952 update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false; in dcn35_calc_blocks_to_gate()
955 update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false; in dcn35_calc_blocks_to_gate()
958 update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false; in dcn35_calc_blocks_to_gate()
961 update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false; in dcn35_calc_blocks_to_gate()
963 update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false; in dcn35_calc_blocks_to_gate()
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_fw_la.h83 cmp_auth, ret_auth, update_state, \ argument
97 ((update_state & QAT_LA_UPDATE_STATE_MASK) << \
/linux/drivers/firmware/arm_scmi/
H A Dprotocols.h227 int (*update_state)(struct scmi_iterator_state *st, member
/linux/drivers/watchdog/
H A Dwm831x_wdt.c31 int update_state; member
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h1239 struct pg_block_update *update_state);
1241 struct pg_block_update *update_state);
1243 struct pg_block_update *update_state);
1245 struct pg_block_update *update_state);
1247 struct pg_block_update *update_state, bool power_on);