Searched refs:ulClock (Results 1 – 5 of 5) sorted by relevance
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di… member449 ULONG ulClock; //When return, [23:0] return real clock member496 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member518 ULONG ulClock:24; //Input= target clock, output = actual clock member520 ULONG ulClock:24; //Input= target clock, output = actual clock529 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member546 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member558 …COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider member571 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member582 …COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider member[all …]
2855 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ in radeon_atom_get_clock_dividers()2869 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ in radeon_atom_get_clock_dividers()2877 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? in radeon_atom_get_clock_dividers()2879 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; in radeon_atom_get_clock_dividers()2923 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ in radeon_atom_get_clock_dividers()2928 dividers->real_clock = le32_to_cpu(args.v4.ulClock); in radeon_atom_get_clock_dividers()2933 args.v6_in.ulClock.ulComputeClockFlag = clock_type; in radeon_atom_get_clock_dividers()2934 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ in radeon_atom_get_clock_dividers()2943 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); in radeon_atom_get_clock_dividers()2944 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in radeon_atom_get_clock_dividers()[all …]
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di… member419 ULONG ulClock; //When return, [23:0] return real clock member462 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member484 ULONG ulClock:24; //Input= target clock, output = actual clock member486 ULONG ulClock:24; //Input= target clock, output = actual clock 495 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member512 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter member523 …COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider member543 ULONG ulClock; member568 ATOM_COMPUTE_CLOCK_FREQ ulClock; member[all …]
2441 u32 ulClock = state->config.clock; in CDRXD() local2545 state->osc_clock_freq = (u16) ulClock; in CDRXD()
973 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock; in vegam_calculate_mclk_params()