Searched refs:ucNumDPMLevels (Results 1 – 10 of 10) sorted by relevance
428 UCHAR ucNumDPMLevels; member435 UCHAR clockInfoIndex[] __counted_by(ucNumDPMLevels);
2705 power_state->v2.ucNumDPMLevels ? power_state->v2.ucNumDPMLevels : 1); in radeon_atombios_parse_power_table_6()2708 if (power_state->v2.ucNumDPMLevels) { in radeon_atombios_parse_power_table_6()2709 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in radeon_atombios_parse_power_table_6()2732 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in radeon_atombios_parse_power_table_6()
1736 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in trinity_parse_power_table()1753 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in trinity_parse_power_table()
1505 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in sumo_parse_power_table()1521 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in sumo_parse_power_table()
2481 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in kv_parse_power_table()2498 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in kv_parse_power_table()
6805 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in si_parse_power_table()6819 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in si_parse_power_table()
5547 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in ci_parse_power_table()5561 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in ci_parse_power_table()
783 size_of_entry_v2(pstate->ucNumDPMLevels)); in get_state_entry_v2()923 for (i = 0; i < pstate_entry_v2->ucNumDPMLevels; i++) { in pp_tables_get_entry()
2744 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in kv_parse_power_table()2761 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in kv_parse_power_table()
7364 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in si_parse_power_table()7378 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in si_parse_power_table()