Searched refs:ucNumDPMLevels (Results 1 – 10 of 10) sorted by relevance
428 UCHAR ucNumDPMLevels; member435 UCHAR clockInfoIndex[] __counted_by(ucNumDPMLevels);
2710 kcalloc(power_state->v2.ucNumDPMLevels ? in radeon_atombios_parse_power_table_6()2711 power_state->v2.ucNumDPMLevels : 1, in radeon_atombios_parse_power_table_6()2716 if (power_state->v2.ucNumDPMLevels) { in radeon_atombios_parse_power_table_6()2717 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in radeon_atombios_parse_power_table_6()2740 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in radeon_atombios_parse_power_table_6()
1737 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in trinity_parse_power_table()1754 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in trinity_parse_power_table()
1506 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in sumo_parse_power_table()1522 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in sumo_parse_power_table()
2482 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in kv_parse_power_table()2499 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in kv_parse_power_table()
5560 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in ci_parse_power_table()5574 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in ci_parse_power_table()
6801 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in si_parse_power_table()6815 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in si_parse_power_table()
784 size_of_entry_v2(pstate->ucNumDPMLevels)); in get_state_entry_v2()924 for (i = 0; i < pstate_entry_v2->ucNumDPMLevels; i++) { in pp_tables_get_entry()
2745 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in kv_parse_power_table()2762 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in kv_parse_power_table()
7313 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in si_parse_power_table()7327 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in si_parse_power_table()