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Searched refs:ubwc_swizzle (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/soc/qcom/
H A Dubwc_config.c22 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
32 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
41 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
55 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3,
64 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
74 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
83 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
93 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
102 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
112 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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/linux/include/linux/soc/qcom/
H A Dubwc.h25 u32 ubwc_swizzle; member
70 if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1)) in qcom_ubwc_get_ubwc_mode()
/linux/drivers/gpu/drm/msm/
H A Dmsm_mdss.c172 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | in msm_mdss_setup_ubwc_dec_20()
187 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | in msm_mdss_setup_ubwc_dec_30()
205 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | in msm_mdss_setup_ubwc_dec_40()
231 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | in msm_mdss_setup_ubwc_dec_50()
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c747 cfg->ubwc_swizzle = 0x6; in a6xx_calc_ubwc_config()
753 cfg->ubwc_swizzle = 0x7; in a6xx_calc_ubwc_config()
786 cfg->ubwc_swizzle = 0x4; in a6xx_calc_ubwc_config()
799 if (cfg->ubwc_swizzle != common_cfg->ubwc_swizzle) in a6xx_calc_ubwc_config()
801 cfg->ubwc_swizzle, common_cfg->ubwc_swizzle); in a6xx_calc_ubwc_config()
820 u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2); in a6xx_set_ubwc_config()
H A Da8xx_gpu.c268 u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2); in a8xx_set_ubwc_config()
269 u32 level3_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL3); in a8xx_set_ubwc_config()
H A Dadreno_gpu.c436 *value = adreno_gpu->ubwc_config->ubwc_swizzle; in adreno_get_param()